Further analysis of the statistical independence of the NIST SP 800-22 randomness tests

Luengo, Elena Almaraz; Olivares, Bittor Alaña; Villalba, Luis Javier García; Hernández-Castro, Julio

doi:10.1016/j.amc.2023.128222

Cited by 2 publications

(5 citation statements)

References 19 publications

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“…The hardware synthesis results show that the proposed architectures operate efficiently within a small FPGA area, achieving high performance in terms of operating frequency and throughput. 19 The results of the analysis using the test suite of NIST on the proposed PRNG indicate that the generated sequences have good statistical behavior and can be used to generate high-quality pseudo-random numbers for real-time applications 20 (Table 4).…”

Section: Nist 800-22 Testmentioning

confidence: 99%

Study and VHDL implementation of a novel chaos-based block cipher algorithm for digital image security

Hajjaji,

Albouchi

2024

J. Electron. Imag.

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We live in an interconnected world, and digital data transmissions have reached significant importance as they are the most used means of communication. Connected objects are widely used in our digital life, yet they may pose vulnerabilities and risks such as hacking or personal data theft due to their often inadequate security. In response to the size and capability restrictions of many existing embedded devices, lightweight cryptography has been considered. This article describes a hardware implementation of the lightweight cryptographic method [very high speed integrated circuit hardware description language (VHDL) and field-programmable gate arrays (FPGAs)]. This work presents a hardware solution for securing digital information, more specifically images, and to ensure a high level of security and favorable performance, a robust algorithm with respect to Shannon's theory, Chaos, and its hardware implementation. The algorithm is a block cipher scheme that treats a block of 128-bit length. The paper discusses the method's two main parts: the key generator-based chaos and the block cipher algorithm that consists of a whitening operation, random permutation, and key-dependent S-box. Both the key generator and the encryption algorithm are implemented using VHDL language on a Xilinx ZedBoard Zynq Development Kit platform. The generated key sequences are tested using the NIST SP 800-22 test suite. The hardware implementation of the proposed algorithm is capable of securing different gray-scale images while maintaining low power usage, a good frequency of 129.9038 MHz, and a high throughput of 1651.201 Mbps. Both statistical and differential attacks demonstrate that the cryptosystem is capable of effective security against the next generation of cryptographic attacks.

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Section: Nist 800-22 Testmentioning

confidence: 99%

Study and VHDL implementation of a novel chaos-based block cipher algorithm for digital image security

Hajjaji,

Albouchi

2024

J. Electron. Imag.

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“…The test focuses on the frequency of all possible m-bit patterns overlapping in the sequence [5,20].…”

Section: 𝑒𝑟𝑓𝑐 𝑓 𝑒𝑥𝑝𝑒𝑐𝑡𝑒𝑑𝑉𝑎𝑙𝑢𝑒 𝐿 √2𝜎mentioning

confidence: 99%

“…The Cusums test focuses on making a cumulative sum where the digits of the entire sequence are set to -1 if it is 0 and +1 when it is 1. This determines whether the sum is very large or very small [1,5,20,23].…”

Section: 𝑒𝑟𝑓𝑐 𝑓 𝑒𝑥𝑝𝑒𝑐𝑡𝑒𝑑𝑉𝑎𝑙𝑢𝑒 𝐿 √2𝜎mentioning

confidence: 99%

“…The test determines the deviation in the number of visits to a particular state. This test is divided into a series of eight states, from which a conclusion must be obtained for each one [1,5,20].…”

Section: The Random Excursions Testmentioning

confidence: 99%

“…The purpose of the test is to detect deviations from the number of visits expected in various states in a random walk. This test has a total of eighteen states [1,5,20].…”

Section: The Random Excursions Testmentioning

confidence: 99%

See 2 more Smart Citations

Design of a New Neuro-generator with Neuronal Module to Produce Pseudorandom and Perfectly Pseudorandom Sequences

Rivas Becerra,

Panduro,

Ortega Cisneros

et al. 2024

Preprint

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This paper presents the design of a new neuro-generator of pseudorandom number type PRNG Pseudorandom Number Generator, which produces complex sequences with an adequate bit distri-bution. The circuit is connected to a neuronal module with six impulse neurons with different be-haviors: spike frequency adaptation, phasic spiking, mixed mode, phasic bursting, tonic bursting and tonic spiking. This module aims to generate a non-periodic signal that becomes the clock sig-nal for one of the LFSRs Linear Feedback Shift Register that the neuro-generator has. To verify its correct operation, the neuro-generator was subjected to a series of tests where the frequencies of the impulse neurons were modified. This modification allows generating a greater number of pulses at the output of the neuronal module, to obtain sequences with different characteristics that pass different NIST statistical tests National Institute of Standards and Technology of U.S. The results show that the new neuro-generator maintains pseudo-randomness in the sequences obtained with different frequencies and it can be implemented on reconfigurable FPGA Field Programmable Gate Array Virtex 7 xc7vx85t-2ffg1761 device. Therefore, it can be used for applications such as biologi-cal systems.

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Further analysis of the statistical independence of the NIST SP 800-22 randomness tests

Cited by 2 publications

References 19 publications

Study and VHDL implementation of a novel chaos-based block cipher algorithm for digital image security

Study and VHDL implementation of a novel chaos-based block cipher algorithm for digital image security

Design of a New Neuro-generator with Neuronal Module to Produce Pseudorandom and Perfectly Pseudorandom Sequences

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