Fuse: A Technique to Anticipate Failures due to Degradation in ALUs

Abella, Jaume; Vera, Xavier; Unsal, Osman S.; Ergin, Oğuz; González, Antonio

doi:10.1109/iolts.2007.34

Cited by 8 publications

(8 citation statements)

References 25 publications

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“…Sharing of the FP units is also reported in AMD's Bulldozer architecture [12] to save area, which validates the principle proposed in [11]. Outsourcing is not a proper solution for integer ALU execution as it occupies a relatively smaller portion of the chip (~1%) but used so frequently [4] that in case of failure, performance penalty is outsized.…”

Section: Introductionmentioning

confidence: 53%

“…Thermal hot-spots are usually addressed with dynamic voltage frequency scaling (DVFS). DVFS subjects the transistors on the chip to increased stress resulting in earlier than expected failure [4]. Aging defects are not present at the time of manufacturing but appear over time.…”

Section: Introductionmentioning

confidence: 99%

“…The execution units that service critical instructions such as INT ALU. These instructions are encountered so frequently [4] that a loss of execution units that service these instructions may have significant performance impact. Redundancy, inherent in a superscalar processor may be used to fix the problem by shutting down faulty units.…”

Section: Introductionmentioning

confidence: 99%

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On graceful degradation of microprocessors in presence of faults via resource banking

Rodrigues

Kundu

2011

2011 IEEE 17th International on-Line Testing Symposium

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Reliability and manufacturability have emerged as -billion transistor chips. In this paper, we investigate how to degrade a chip multiprocessor (CMP) gracefully in presence of faults, by keeping its architected functionality intact at the expense of some loss of performance. The proposed solution involves banking resources and functional units that allow partial shutdown to isolate faulty regions. Within a processor chip, resources can be classified into three broad classes, namely the large memory structures such as caches, TLB, register file, the small memory structures namely the reorder buffer, issue queue, load-store buffer etc. and the datapath and control logic. The large arrays are usually well protected by ECC. Recent research has suggested that large datapath units such as FPU and integer division units are good candidates for execution outsourcing to other working cores in CMP. In this paper, we focus on relatively small but critically important integer ALU unit and small array structures. Outsourcing ALU operations incur large performance penalty and small arrays are critical for control operations. The proposed solution is based on banking of array structures and execution units as well as reducing instruction fetch, issue and retire widths that allow individual bank(s) to be disabled for operation. Reduction in resource size diminishes performance but retains functionality. In this paper we present performance degradation data for shutting down one or more banks for various small array structures and ALU units. Simulation confirms gradual degradation with diminishing resource sizes. On average over all considered structures, performance loss of just 6% was observed for single bank failures.

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Section: Introductionmentioning

confidence: 53%

Section: Introductionmentioning

confidence: 99%

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On graceful degradation of microprocessors in presence of faults via resource banking

Rodrigues

Kundu

2011

2011 IEEE 17th International on-Line Testing Symposium

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“…A similar scheme was presented by Rodrigues et al in [15]. Fault detection in integer ALU execution units is proposed by Abella et al in [10]. Self test for register data flow is proposed by Carretero et al in [13].…”

Section: Prior Researchmentioning

confidence: 97%

“…As a result, fault detection and correction schemes have been a topic of considerable interest. Previous approaches may be classified into those that target certain structures in a processor ( [5], [10], [13], [14], [15]) and those that target the entire processor ( [1], [2], [3] , [9], [11], [12], [31], [35], [36]). Of these a few of them are directly comparable to our approach.…”

Section: Prior Researchmentioning

confidence: 99%

An Architecture to Enable Life Cycle Testing in CMPs

Rodrigues¹,

Koren²,

Kundu³

2011

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

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CMOS wear-out mechanisms such as time dependent breakdown of gate dielectrics (TDDB), hot carrier injection (HCI), negative bias temperature instability (NBTI), electromigration (EM), and stress induced voiding (SIV) are well documented in the literature. Often the onset of wear-out is gradual, with initial manifestation as delay defects that result in timing errors. This motivates the need for online testing. The combined effect of dynamic reconfiguration such as voltage and frequency scaling (DVFS) and signal integrity issues coupled with aging related wear-outs complicate a priori selection of test vectors, further favoring online testing. Traditional online test techniques such as Double and Triple Modular Redundancy (DMR and TMR) pose severe area and power overheads. In this paper we propose an architecture to assist online testing in a Chip Multiprocessor (CMP) based on execution path recording. Since in practice, core utilization in CMPs is low, we can use the idle time of cores opportunistically to run test threads that mimic functional threads. The initiation, termination and comparison of test results is performed by a dedicated, simple and functionally limited small core that we call the Sentry Core (SC). The sentry core is hidden from the OS and has the ability to monitor and interrupt the general-purpose cores. Upon interrupt, the general-purpose core can send data to the sentry core. To detect errors, the SC initializes the general-purpose cores and collects signatures from hardware monitors (that compact execution traces) and compares them against duplicate test threads, obviating any need for cycle by cycle comparison. Major benefits of the proposed solution include: (1) online testing with minimal area overhead, (2) scalability, and (3) testability throughout the life cycle of a CMP. Experimental results show that the proposed scheme is capable of detecting 87% of the faults injected into the processor at an area overhead of less than 3% of the target CMP.

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