Future challenges of flash memory technologies

Two-dimensional (2D) atomic crystals are attractive for use in next-generation nanoelectronics, due to their unique performances, which may lead to the resolution of the technological and fundamental challenges in semiconductor industry. Based on the introduction of 2D atomic crystal-based transistors and ambipolar behavior, the review presents a brief summary of 2D atomic crystal integration circuits, including memory, logic gate, amplifier, inverter, oscillator, mixer, switch and modulator. The devices show promising performances for the application in future nanoelectronics. In particular, the 2D atomic crystals, such as graphene, demonstrate good compatibility with the existing semiconductor process. The quaternary digital modulations have been achieved with flexible and transparent all-graphene circuits. Moreover, the heterojunction based on 2D atomic crystals may enable new devices beyond conventional field-effect transistors. The results make us be optimistic that practical 2D atomic crystal technologies with complex functionality will be achieved in the near future. Therefore, 2D atomic crystals are paving new ways for nanoelectronics.

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“…[94][95][96][97] Graphene flash memory (GFM) has been fabricated, exhibiting a wide memory window at low voltage, as shown in Fig. 4a and b.…”

Section: Electronic Circuitsmentioning

confidence: 99%

Two-Dimensional Atomic Crystals: Paving New Ways for Nanoelectronics

Fan

Djerdj

2015

Journal of Elec Materi

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“…Nevertheless, there are three critical limitations that prevent further technology scaling on FG flash memory, i.e. (1) severe stress induced leakage current (SILC) triggered if the tunnel oxide layer is scaled to less than 8 nm; (2) gate coupling ratio of minimum 0.6 has to be met in order for control gate of FG flash memory to properly exert control to FG and the channel; (3) severe cellto-cell interference [1][2][3][4][5][6][7][8]. As compared to FG flash memory, NBCTF memory enables better downscaling of the tunnel oxide layer while still preserving overall good data retention performance.…”

Section: Introductionmentioning

confidence: 99%

“…Tunnel oxide nitridation (TON) is one of the approaches applied together with the downscaling of tunnel oxide layer in order to enhance the immunity of NBCTF memory to Fowler-Nordheim (FN) stress induced damages in tunnel oxide layer. By implementing various wet or dry nitridation processes, TON is done by incorporating nitrogen content into the tunnel oxide layer to achieve larger memory window and better hardening towards the damages due to extensive program/erase P/E) cycling stress through FN injection [1][2][3][4][5][6][7][8][9][10]. Nevertheless, TON was also found to result in several critical reliability issues such as Fermi-level defects and mid-gap defects.…”

Section: Introductionmentioning

confidence: 99%

Investigation on the origin of the anomalous tail bits on nitrided charge trap flash memory

Lee

Wong

2015

Microelectronics Reliability

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“…Scaling the FG cell size much below than 30 nm is unlikely as several scaling challenges are anticipated, solutions to which are still unknown [4]. The key issues facing FG technology today are the following: 1) scaling of the tunnel oxide (TO) and interpoly dielectric thickness; 2) scaling of the lateral dimensions which increases coupling between the adjacent cells; and 3) the loss of control gate (CG)-FG coupling due to the planar FG structure required at sub-30-nm dimensions [5].…”

Section: Introductionmentioning

confidence: 99%

Performance and Reliability Study of Single-Layer and Dual-Layer Platinum Nanocrystal Flash Memory Devices Under NAND Operation

Singh

Bisht

Auluck

et al. 2010

IEEE Trans. Electron Devices

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Abstract-Memory window (MW) and the retention of singlelayer (SL) and dual-layer (DL) platinum (Pt) nanocrystal (NC) devices are extensively studied before and after program/erase (P/E) cycling. DL devices show better charge storage capability and reliability over the SL devices. Up to 50% improvement in the stored charge is estimated in the DL device over SL when P/E is performed at equal field. Excellent high temperature and postcycling retention capabilities of SL and DL devices are shown. The impact of the interlayer film (ILF) thickness on the retention of the DL structure is reported. While SL devices show poor P/E cycling endurance, DL cycling is shown to meet the minimum requirements of the multilevel cell (MLC) operation.

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Future challenges of flash memory technologies

Cited by 153 publications

References 5 publications

Two-Dimensional Atomic Crystals: Paving New Ways for Nanoelectronics

Two-Dimensional Atomic Crystals: Paving New Ways for Nanoelectronics

Investigation on the origin of the anomalous tail bits on nitrided charge trap flash memory

Performance and Reliability Study of Single-Layer and Dual-Layer Platinum Nanocrystal Flash Memory Devices Under NAND Operation

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