Future directions for DRAM memory cell technology

Nitayama, A.; Kohyama, Y.; Hieda, K.

doi:10.1109/iedm.1998.746373

Cited by 29 publications

(17 citation statements)

References 1 publication

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“…A RAM cell (a) uses three transistor dynamic random access memory (DRAM) scheme; however, four-transistor static RAM (SRAM) scheme can also be applied. Conventional one-transistor one-capacitor memory cell currently used in MOS DRAMs [56] would not be suitable for molecular memories, because of the difficulty in sustaining large capacitance in a molecule. ROM cell (b) stores charge in the gate region of the control transistor.…”

Section: ) Switching Using Single Electron Transfer Principlesmentioning

confidence: 99%

Prospects for single molecule information processing devices

Wada

2001

Proc. IEEE

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Present information technologies use semiconductor devices and magnetic/optical discs; however, they are all foreseen to face fundamental limitations within a decade. Therefore, superseding devices are required for the next paradigm of high-performance information technologies. "Single molecule devices" have been expected to be the most probable candidate; however, they have not been made practical since they were first proposed more than a quarter of a century ago. The major obstacles are the extreme difficulty in accessing a single molecule, and the very complicated electron states of a molecule connected to electrodes. With the advancements in scanning tunneling microscope (STM) and simulation technologies, the design and demonstration of single molecule devices are close to reality. This paper first reviews the architectures suitable for single molecule information processing, in which it is claimed that the performances of information processing is higher, if speed and element number product is larger in almost all architectures. Then, prospects for single molecule devices, including switching devices, wires, diodes, nanotubes, optical devices, storage devices and sensing devices for future information technologies and other advanced applications are described. Four milestones for realizing the peta/exa-floating operations per second (FLOPS) personal molecular supercomputer are proposed. Current status and necessary technologies of the first milestone are described, and necessary technologies for the next three milestones are also discussed.

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Section: ) Switching Using Single Electron Transfer Principlesmentioning

confidence: 99%

Prospects for single molecule information processing devices

Wada

2001

Proc. IEEE

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“…As the device dimensions are scaled down, the capacitance volume is reduced and the restore electric charge is decreased. Both stacked capacitor (STC) cell and trench capacitor (TRC) cell can help to solve this problem [1], but their fabrication processes are too complex to scale down. Hence, the SOI 1T-DRAM was proposed due to its capacitorless structure with simple process, low fabrication cost, and increased integrated density [2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Reliability analysis of a new vertical MOSFET with bMPI structure for 1T-DRAM applications

Chen

Lin

et al. 2010

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

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We present a reliability analysis of a new vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM applications. The proposed 1T-DRAM device can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved by about 95% when compared to the planer bMPI 1T-DRAM. Owing to the double-gate structure, vertical bMPI has great gate controllability over the channel region; hence, it can reduce the short-channel effects (SCEs) and enhance the current drive. And the VbMPI 1T-DRAM cell can keep holes in nature body region, which leads to an increase in data retention time.

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“…Present DRAM chips in production integrate a 1-transistor, 1-capacitor (1T/1C) cell having an area of 8 [1]. Experimental 1T/1C cells having an area of 6 or even 4 have been proposed [2], [3], but for all 1T/1C cells, the main challenge in cell area reduction lies with the capacitor integration. Indeed for each memory generation, a constant capacitance value of 30 fF/cell is targeted [4].…”

Section: Introductionmentioning

confidence: 99%

A capacitor-less 1T-DRAM cell

Okhonin

Nagoga

Sallèse

et al. 2002

IEEE Electron Device Lett.

214

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A simple true 1 transistor dynamic random access memory (DRAM) cell concept is proposed for the first time, using the body charging of partially-depleted SOI devices to store the logic "1" or "0" binary states. This cell is two times smaller in area than the conventional 8 2 1T/1C DRAM cell and the process of its manufacturing does not require the storage capacitor fabrication steps. This concept will allow the manufacture of simple low cost DRAM and embedded DRAM chips for 100 and sub-100 nm generations.

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Future directions for DRAM memory cell technology

Cited by 29 publications

References 1 publication

Prospects for single molecule information processing devices

Prospects for single molecule information processing devices

Reliability analysis of a new vertical MOSFET with bMPI structure for 1T-DRAM applications

A capacitor-less 1T-DRAM cell

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