In this paper, a CMOS wide-band second-order voltage-mode allpass filter as a time delay cell is proposed. The proposed all-pass filter is made up of solely two transistors as active elements and four passive components. This filter demonstrates a group delay of approximately 60 ps within a bandwidth of 5 GHz, achieving maximum delay-bandwidth-product (DBW). The proposed circuit is highly linear and has an input-referred 1-dB compression point P 1dB of 2 dBm. The power consumption of the proposed circuit is only 10.3 mW. On the other hand, an active inductor is employed in the all-pass filter instead of a passive RLC tank, thereby the three passive components are eliminated, in order to tune the time delay and improve the size. In this case, even though the power consumption increases, the time delay can be controlled across an improved bandwidth of approximately 10 GHz. Moreover, the circuit demonstrates a 1-dB compression point P 1dB of 18 dBm. The proposed all-pass filter is simulated in TSMC 180-nm CMOS process parameters.