Tunable Active Inductor-Based Second-Order All-Pass Filter as a Time Delay Cell for Multi-GHz Operation

Aghazadeh, Seyed Rasoul; Sarmiento, Fredy Hernán Martínez; Saberkari, Alireza; Alarcón, Eduard

doi:10.1007/s00034-019-01032-1

Cited by 20 publications

(13 citation statements)

References 20 publications

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“…By substituting the above three equations in (16), and after some simplifications, the overall NF of the second path is:…”

Section: The Noise Performance Of Ttd Cellmentioning

confidence: 99%

“…Unfortunately, the inductor-based TTD cells are in contrast with these characteristics. Hopefully, some designs presented inductor-less TTD cells for addressing this matter [9,16].…”

Section: Introductionmentioning

confidence: 99%

“…Delay lock loop (DLL) and master-slave circuit are system-level approaches to have a flat wideband delay [18,19]. It shows the reason for the high DV in previous works (more than 10% DV for over 25 ps delays) in the frequency band [13,15,16]. In this paper, a circuit-level approach is introduced to address this issue.…”

Section: Introductionmentioning

confidence: 99%

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A PVT resilient true‐time delay cell

Yarahmadi

Jannesari

2023

IET Circuits, Devices & Syst

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A true-time delay (TTD) cell in TSMC 0.18 μm CMOS technology for 1-5 GHz applications is presented. Process variations, ageing effects, field variations, and other non-idealities have some impacts on the TTD cell's devices. One of the vulnerable specifications of TTD cells is their delay variation. While the TTD cell works in a delay line, the cell must have a constant and robust delay in the frequency band. For this matter, the body bias technique is presented and applied to the inductor-less TTD cell. With this technique, the threshold voltage can be manipulated intentionally. So, any variation in this voltage can be compensated with the body biasing of transistors. The simulation results show the TTD cell's robust performance against non-idealities, while delay variation improves more than 3� times in the frequency band of interest. This TTD cell provides a 50.95 pS delay with only 2% variation, while S 11 and S 22 parameters are lower than −10 dB in the 1-5 GHz frequency band. IIP3 of the TTD cell is about 2.7 dBm, and the power consumption is 20.5 mW. K E Y W O R D Sall-pass filter, active filters, analogue integrated circuits, CMOS analogue integrated circuits, continuous time systems, integrated circuit design, low-power electronics, radio frequency filters, Timed array system, True-Time-Delay cellThis is an open access article under the terms of the Creative Commons Attribution-NonCommercial-NoDerivs License, which permits use and distribution in any medium, provided the original work is properly cited, the use is non-commercial and no modifications or adaptations are made.

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“…By substituting the above three equations in (16), and after some simplifications, the overall NF of the second path is:…”

Section: The Noise Performance Of Ttd Cellmentioning

confidence: 99%

“…Unfortunately, the inductor-based TTD cells are in contrast with these characteristics. Hopefully, some designs presented inductor-less TTD cells for addressing this matter [9,16].…”

Section: Introductionmentioning

confidence: 99%

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A PVT resilient true‐time delay cell

Yarahmadi

Jannesari

2023

IET Circuits, Devices & Syst

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“…With regard to (7), for a given inductance and quality factor, the input-referred current noise of the circuit is minimised by choosing appropriate g m3 and g m1,a . In other words, the noise due to M 3 is reduced by decreasing g m3 that for a given current is limited by the maximum voltage headroom [12], and choosing higher g m1,a (i.e.…”

Section: F I G U R E 5 Low Noise Ai With Noise Cancellation Techniquementioning

confidence: 99%

“…A self-biased AI [6][7][8][9] that comprises one transistor and a resistor is shown in Figure 4. The inductance is realised by using the gate-source capacitance of M 1 , the resistor R, and the transconductance of M 1 .…”

Section: Literature Reviewmentioning

confidence: 99%

A low‐noise current‐reused CMOS active inductor by exploiting G _m ‐boosting technique

Ebrahimi

2021

IET Microwaves Antenna & Prop

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This work introduces a new low‐noise current‐reused CMOS active inductor (AI) based on Gyrator‐C configuration. In the proposed AI, a simple common‐source amplifier is utilised for boosting effective Gm and improving noise performance of the AI. While the Gm‐boosting technique improves the noise performance as well as the quality factor of the inductor, a resistor is also added to the feedback path for more quality factor improvement. Rigorous analysis of the proposed circuit shows a significant noise performance and quality factor enhancement. In order to verify the concept and confirm the mathematical analysis, the AI is designed and simulated in a commercial 0.18 μm RF‐CMOS technology. The simulation results show that the proposed inductor operates in 1 to 7.2 GHz frequency range, has a 9 nH inductance at 2.864 GHz frequency and 650 μW total power dissipation at 1.8‐V supply voltage. Maximum quality factor of 90 is achieved at 2.864 GHz frequency and a quality factor greater than 40 is obtained from 2.4 to 3.3 GHz. The input‐referred current noise of the proposed inductor is as low as 22 pA/√Hz showing 30.5% improvement compared to the conventional AI. The proposed AI is also tunable and sweeping the tuning voltage results in changing extracted inductance from 4.35 to 15.2 nH with only a chip area of 0.003 mm2. Post‐layout and different Monte Carlo simulation results also confirm the robust operation of the proposed AI against different process non‐idealities.

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Wideband third‐order single‐transistor all‐pass filter

Elamien

Maundy

Belostotski

et al. 2020

Circuit Theory & Apps

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SummaryIn this letter, a third‐order wideband voltage‐mode all‐pass filter (APF) is proposed for application as a true time delay (TTD) cell. The advantages of designing a single‐stage higher order filter over cascading several lower order stages are illustrated. The proposed APF circuit is based on a single metal‐oxide‐semiconductor (MOS) transistor and is canonical because it requires one resistor, one inductor, and two capacitors. To the best of the authors' knowledge, this is the first single‐transistor third‐order APF circuit to be reported in the literature. The operation of the proposed APF is validated through post‐layout simulations in a 65‐nm CMOS technology. The simulation results demonstrate a group delay of 59.4 ps across a 13.2‐GHz bandwidth with a maximum delay‐bandwidth product of 0.783, while consuming only 3.54mW from a 1‐V supply voltage. Moreover, the designed circuit achieves an input‐referred IP3 of 19.95 dBm and occupies an area of 161.5μm × 204.8μm.

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Tunable Active Inductor-Based Second-Order All-Pass Filter as a Time Delay Cell for Multi-GHz Operation

Cited by 20 publications

References 20 publications

A PVT resilient true‐time delay cell

A PVT resilient true‐time delay cell

A low‐noise current‐reused CMOS active inductor by exploiting G _m ‐boosting technique

Wideband third‐order single‐transistor all‐pass filter

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Tunable Active Inductor-Based Second-Order All-Pass Filter as a Time Delay Cell for Multi-GHz Operation

Cited by 20 publications

References 20 publications

A PVT resilient true‐time delay cell

A PVT resilient true‐time delay cell

A low‐noise current‐reused CMOS active inductor by exploiting G m ‐boosting technique

Wideband third‐order single‐transistor all‐pass filter

Contact Info

Product

Resources

About

A low‐noise current‐reused CMOS active inductor by exploiting G _m ‐boosting technique