Gain and frequency controllable sub-1 V 5.8 GHz CMOS LNA

Abstract

This paper presents the design and experimental results of a low-voltage low noise amplifier (LNA) with gain and frequency control in a standard 0.18 pm CMOS process. Targeting at a center frequency of 5.8 GHz with a supply voltage of 1 V, the LNA exhibits a power gain of 13.2 dB with a noise figure of 2.5 dB. The circuit has over 10 dB of gain tuning, and 360 M H z of frequency tuning, and can operate at a supply voltage as low as 0.7 V.

A 1 V switchable CMOS LNA for 802.11A/B WLAN applications

“…The switchable LNA demonstrates an in-band input IIP3 of −8.9 dBm and −5.7 dBm, and in-band CP1 of −17.98 dBm and −14.94 dBm at 2.4 and 5.2 GHz, respectively. The overall performance of the proposed LNA could give a similar or even better, in power consumption and noise figure, results compared [2,5], except some deterioration in the linearity.…”

Current status of CMOS low voltage and low power wireless IC designs

“…5(a) [48][49][50] The main idea behind this low-voltage topology is the ability to decouple the AC and DC currents between the two transistors, hence allowing the reduction of the voltage supply to less than 1 V, while avoiding pushing the transistors close to the triode region. To ensure that the circuit operates as a cascode amplifier, the entire RF signal current (g m1 v gs1 ) [48][49][50], and (b) modified folded cascode [51,52] generated by M1 should be fed into the source of M2 (i.e. driving ≈ 1/g m2 ).…”

“…in SOI CMOS) may increase the popularity of this topology Another promising low voltage LNA architecture is the folded cascode topology shown in Fig. 5(b) [51,52]. Historically, the use of PMOS devices in RF circuits was not common due to their lower f T 's, compared to their NMOS counterparts.…”

“…5(b) is borrowed from the conventional folded cascode topology of CMOS operational amplifiers, with modifications making it suitable for low-voltage RF applications. A detailed analysis can be found in [52]. One inherent advantage of this topology, over other architectures, is its potential to allow gain controllability by adjusting the gate voltage (V ctl ) of the PMOS transistor M2, which can result in overall linearity improvement.…”

“…A reasonably low noise figure (e.g. < 3 dB) can be achieved with gain controllability using this topology [52]. Conventional cascode amplifiers do not have this flexibility, since stacked transistors share the same DC current.…”