Gain‐boosted dynamic amplifier for pipelined‐SAR ADCs

Abstract

A high-gain and high-speed gain-boosted dynamic amplifier for pipelined-successive approximation register ADCs is presented. A cross-coupling cascode topology is proposed to boost the gain of a single-stage dynamic amplifier. The proposed dynamic amplifier achieves a voltage gain of 32 under a 1.2 V power supply in 130 nm CMOS technology. Sampling at 150 MS/s, the proposed dynamic amplifier consumes a total power of 0.22 mW.

High‐gain and power‐efficient dynamic amplifier for pipelined SAR ADCs

“…Hence, a large V ov is preferred for linearity. However, the noise becomes worst when V ov is large as shown in (5). This trade-off between linearity and noise holds for all dynamic amplifiers.…”

“…By having a complementary input and a reference level detector (RLD), a high gain, LNA is made possible. The proposed amplifier consumes less energy than other dynamic amplifiers [1][2][3][4][5], resulting in an improvement of the pipelined SAR ADC efficiency.…”

A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain

“…The RA can reduce the input referred noise of the second SAR ADC, thus greatly relaxing its design burden and decreasing its power. A dynamic residue amplifier (DRA) is usually employed due to its simple structure and zero static power [15][16][17][18]. In a dynamic amplifier, the output voltage swing needs to be kept in a small range to obtain relatively high linearity.…”