GARDA: a diagnostic ATPG for large synchronous sequential circuits

Corno, Fulvio; Prinetto, P.; Rebaudengo, Maurizio; Reorda, M. Sonza

doi:10.1109/edtc.1995.470385

Cited by 28 publications

(4 citation statements)

References 10 publications

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“…Under the point of view of the fault coverage (FC) and diagnostic resolution (DR) [9], results obtained on the processor and arithmetic core by exploiting the adopted SoC test structures are the reported in table I. Memory cores test and diagnosis consist in the application of 22n STMicroelectronics march test that covers and allows the diagnosis of SAF, TF, SOF, DRF, AF, CF, UWF, WTF [8].…”

Section: Case Study and Experimental Resultsmentioning

confidence: 99%

An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs

Appello

Bernardi

Cagliesi³

et al. 2008

2008 13th European Test Symposium

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This paper describes a novel approach to enhance the process of reliability characterization for VLSI SoC products. To do this, we exploit Design for Test and Diagnosis structures in combination with new low-cost tester features and architecture. The main focus of our work is to obtain a modeling of the degradation of selected parameters measurable through at-speed testing.The paper reviews the current approach for reliability characterization and shows the achieved enhancement on efficiency and effectiveness. Results shown are related to experiments run on a vehicle released on a 90nm technology.

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Section: Case Study and Experimental Resultsmentioning

confidence: 99%

An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs

Appello

Bernardi

Cagliesi³

et al. 2008

2008 13th European Test Symposium

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“…Adding and testing additional paths to facilitate diagnosis for static faults is not a new concept [7], [8]. Essentially it produces new test patterns by constraining ATPGs to differentiate faults.…”

Section: Introductionmentioning

confidence: 99%

Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method

Chen

Liou

2006

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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In this paper, we apply a technique to improve diagnosis resolution for delay faults. The method analyze the structure of test paths to find the bottleneck of the diagnosis process. Then we use the information to search for additional paths (by extending from the current paths) in order to effectively cut down the number of faulty candidates. The experimental result shows that the proposed technique can reduce the efforts of diagnosis by a meaningful amount. In ISCAS'89 benchmarks, the method can improve the average ranks of injected defects in the suspect list from 9.14 to 5.97 as injected delay size is 1% of longest paths.

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“…Diagnostic tests are generated by a diagnostic test generation procedure [22][23][24][25][26][27][28][29][30][31][32][33][34][35]. The goal of diagnostic test generation is to distinguish pairs of faults.…”

Section: Introductionmentioning

confidence: 99%

Improving the accuracy of defect diagnosis by adding and removing tests

Pomeranz

2016

IET Computers & Digital Techniques

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An augmented defect diagnosis procedure removes tests from consideration in order to improve the accuracy of defect diagnosis by reducing the number of candidate faults. This work studies the role of diagnostic test generation in this context. Diagnostic test generation increases the number of tests that are used for defect diagnosis in order to increase its accuracy. The combined effect of using diagnostic test generation and the augmented defect diagnosis procedure is to add and remove tests in order to improve the accuracy of diagnosis. This study suggests a flow for a two-phase defect diagnosis process that combines the two procedures. Some of the issues that arise, and are addressed by this study, are: (i) which faults to target during diagnostic test generation, (ii) how to restart the augmented defect diagnosis procedure after diagnostic test generation, and (iii) how many of the diagnostic tests the augmented defect diagnosis procedure will remove.

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GARDA: a diagnostic ATPG for large synchronous sequential circuits

Cited by 28 publications

References 10 publications

An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs

An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs

Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method

Improving the accuracy of defect diagnosis by adding and removing tests

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