Gate chain structures with on-chip clock generators for realistic high-speed dynamic stress

Shiono, Noboru; Mizusawa, T.

doi:10.1109/icmts.1990.161755

Cited by 2 publications

(1 citation statement)

References 5 publications

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“…These test structures were also used to investigate circuit reliability caused by hotcamer-induced degradation of MOSFETs under realistic dynamic stress conditions [1,2]. To evaluate, however, reliable dynamic circuit performance, it needs a combination of an inverter chain, a ring oscillator and a single device [3].…”

Section: Introductionmentioning

confidence: 99%

A combined test structure with ring oscillator and inverter chain for evaluating optimum high-speed/low-power operation

Matsuda

Iwata

Ohzone³

et al.

International Conference on Microelectronic Test Structures, 2003.

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A test structure combined with a ring oscillator, an inverter chain and an embedded monitor inverter, which allows accurate internal node access, is proposed. Vdd and well-hias dependence of gate delay and supply current measured hy both ring oscillator and inverter chain scheme. V, control method by well biasing, particularly to forward direction, is effective for high speed operation under low supply voltage. The new test structure can he utilized to evaluate optimum conditions for high-speed/low-power operations as well as high-reliability operations.

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Section: Introductionmentioning

confidence: 99%