Gate current dependent hot-carrier-induced degradation in LDMOS transistors

Investigating Reliability and Stress Mechanisms of DC and Large-Signal Stressed CMOS 65-nm RF-LDMOS by Gate Current Characterization

“…From the induced defects follows a high drift in I dQ (@V g /V d =2V/3.3V) of -29 % after 26 hours, see Fig. 6a but also G mlin degrades (-19 %), due to the mobility decrease caused by scattering mechanisms [9]. The drift of all of these parameters are large compared to the drift of R ON (+4.3 %) since R ON is not only attributed the channel, but also the drift region and the drain extension combined.…”

“…The drift of all of these parameters are large compared to the drift of R ON (+4.3 %) since R ON is not only attributed the channel, but also the drift region and the drain extension combined. The defects are only induced in the oxide underneath the gate which causes R ON to have an apparently overall lower drift [9,10]. Calculation of R ON was compensated for threshold voltage which gives a more adequate picture of the mobility decrease.…”

“…In literature, this has been studied but only at specific voltages interesting for e.g. inducing hot carriers [9][10][11]. In terms of actual PA operation of the transistors, the voltage swings along a load line.…”

Characteristics of Lateral Diffused Metal–Oxide–Semiconductor Transistors with Lightly Doped Drain Implantation through Gradual Screen Oxide

“…Thus, higher V G bias during stressing results in more electron injection to the gate oxide, leading to more device degradation. 32) Finally, the E-SOA of devices with traditional and gradual junction profiles is investigated. Figure 9 depicts the measurement setting to obtain E-SOA, where different dc V G bias (3, 5, 8, 9, 10, and 12 V) and 100 ns pulse of ramped V D with 0.1 V in each step are applied to the device.…”

Comparisons of hot-carrier degradation behavior in SOI-LIGBT and SOI-LDMOS with different stress conditions

“…As a result, the lateral insulated gate bipolar transistor on SOI substrate (SOI-LIGBT) begins to be a promising power device for power IC's applications due to its combination the high input impedance of MOS gate and the conductivity modulation effect of bipolar transistor, which can solve the contradiction between BV and R on well. However, a severe drawback of the above both lateral devices is that the current is flowing along the Si/SiO 2 interface making the devices vulnerable to hot-carrier injection and trapping, lots of papers have reported the hot-carrier degradation for LDMOS devices [3][4][5][6], but the hot-carrier degradation for SOI-LIGBT devices is less documented. In practice, the current of SOI-LIGBT is composed of electron current along the surface of the device and hole current in the body of the silicon film above buried oxide layer.…”