Gate Drive Circuit Implementation for Parallel Connection of Power Devices Considering Parasitic Inductance

Abstract

SiC devices are potential future power devices because of their higher switching speed and lower ON resistance than those of Si devices. Research and development efforts to apply them in medium-and largecapacity power conversion circuits are underway. However, SiC power devices in TO packages, which are general-purpose packages, are difficult to apply in high-current applications owing to their low current ratings. Therefore, increasing the capacity of power devices by connecting them in parallel is being studied. However, the current imbalance during switching due to the differences in device characteristics and variations in parasitic inductance is problem. This study proposed a current-balancing procedure focused on the parasitic inductances around power devices and gate drive circuit implementation. The proposed method was verified by conducting double-pulse tests at 300 V and 200 A.

Loss and Temperature Evaluation of Unbalanced Three‐Phase Inverter Driven Two‐Phase PWM Scheme Using Variable Switching‐Pause Period

“…[10] proposed a motor drive without high harmonic generation. To overcome the effects of these variations, some methods have been proposed to reduce the imbalance in the switching losses by improving the gate-drive circuit [9,11,12]. This paper is based on Reference (15), which was published in the proceedings of the technical meetings of SPC/HCA/VT (2022) © 2022 IEEJ.…”

“…[10] proposed a motor drive without high harmonic generation. To overcome the effects of these variations, some methods have been proposed to reduce the imbalance in the switching losses by improving the gate‐drive circuit [9,11,12].…”