Gate-driven 3.3V ESD clamp using 1.8V transistors

Abstract

A new gate driven 3.3V ESD clamp circuit using 1.8V transistor is proposed. This new clamp circuit is suitable for ESD protection of legacy 3.3V I/O interface circuit in SOC chips which use only 1.8V I/O transistors. This clamp along with 3.3V I/O have been demonstrated in 40nm 1.8V process. Life-time test can pass 1000-hours prolonged operation. ESD/Latch-up can pass HBM 3KV, MM 300V, and +/-200mA current triggering and 4.95V (1.5 x VDD) over-voltage test. Index Terms-gate-driven, gate oxide over-stress, human-body model (HBM), machine model (MM)