Gate Failures Effectively Shape Multiplexing

Abstract

This paper investigates the behavior of multiplexing (MUX) schemes in combination with the elementary gates. The two schemes under investigation are majority (MAJ) and NAND MUX. The simulation results presented here are for single-electron technology, but could easily be extended to CMOS. The components of the gates have been subjected only to geometric variations. Firstly, the gates and the two MUX schemes are analyzed theoretically. Secondly, simulations using probability transfer matrices (PTM) allow evaluating both MUX schemes at a redundancy factor R = 6. Finally, the gates are compared in terms of their intrinsic probability of failure (with respect to geometric variations), and the two MUX schemes are weighted against the reliability enhancements they are bringing into the system. By comparing the simulation results from PTM with the ones based on (geometric) variations, this study gives deeper insights into the behavior of MUX schemes, and show that the gates play a major role, strongly affecting MUX systems.

Proxels for Reliability Assessment of Future Nano-Architectures

“…This is an alternative to the well-known discrete-event simulation. As shown in [10], failures that appear in nano-circuits cannot typically be modelled using exponential distributions. In fact, in [4], it was shown that the lognormal distribution is much more adequate for describing device failures, as opposed to the memoryless alternative, i.e., the exponential distribution (which has been in use for quite some time).…”

Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing

“…However, when taking into account the devices forming the gates, this result can change, e.g., it can reverse in certain cases when using single-electron technology [10]. Reliability analyses were made for NANDand MAJ-based multiplexing schemes with low and medium redundancy factors (3 to 3000), using various methods to compute or estimate the system reliability: analytical modelling [11], [12], [8], [9], [13], probability transfer matrix [14], [10], probabilistic model checking [15], [16], Monte Carlo simulations [10], [17] or Bayesian networks [18].…”

“…All of the above mentioned works consider that gates fail with the same probability, with the exception of [10], where the gates are implemented in Single-Electron Tunnelling (SET) technology, and [17], [18], where manufacturing variability effects on the multiplexing scheme are investigated. Our work also considers gates failing with different probabilities, but from a different perspective, and as an effect of a different Figure 2: Multiplexing unit reliability contribution in a highly faulty system.…”

Reliability the Fourth Optimization Pillar of Nanoelectronics

“…This means that the probabilities of failure are independent of the length of time the gates and devices have been in use. Conversely, it has been shown that the exponential behavior of failures is incorrect and produces significant error that cannot be ignored [3].…”