Gate induced drain leakage reduction with analysis of gate fringing field effect on high-κ/metal gate CMOS technology

Jang, Esan; Shin, Sunhae; Jung, Jae Won; Kim, Kyung Rok

doi:10.7567/jjap.54.06fg10

Cited by 7 publications

(4 citation statements)

References 29 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…insulator of Pi-FinFET, as shown in Figure 3b. Namely, the rather constant electric field in the buried insulator of Pi-FinFET induces a wider PDW near the drain region [12]. The dotted red ellipse in Figure 3b shows that the PDW is wider in the silicon layer compared to the conventional S-FinFET.…”

Section: Resultsmentioning

confidence: 92%

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

et al. 2018

View full text Add to dashboard Cite

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited four times lower I off than modified S-FinFET, called RFinFET, with more improved drain-induced barrier lowering (DIBL) characteristics, while minimizing I on reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved drain-induced barrier lowering (DIBL) and I off characteristics as gate channel length decreased.Keywords: gate-induced drain leakage (GIDL); drain-induced barrier lowering (DIBL); recessed channel array transistor (RCAT); on-current (I on ); off-current (I off ); subthreshold slope (SS); threshold voltage (V TH ); saddle FinFET (S-FinFET); potential drop width (PDW); shallow trench isolation (STI); technique for the buried insulator under the cell transistor [7,8]. We analyzed electrical characteristics of this proposed device and compared them with those of conventional S-FinFETs of the same size. We also showed the optimized parameters of the buried insulator using a three-dimensional (3D) device simulator in sub-30 nm cell size [9]. The device described in this paper has reliable source/drain (S/D) doping concentration with a Gaussian profile. The simulator is well tuned to predict DRAM cell transistor leakage distribution [10,11]. Device StructureThe partial isolation type S-FinFET (Pi-FinFET) is a structure with a buried insulator at a certain depth from the storage node of a conventional S-FinFET. Figure 1a shows a 3D schematic of a Pi-FinFET. Silicon film thickness, buried insulator thickness, and L in , as shown in Figure 1a,b, are defined as the distance from the contact surface of the storage node to the buried insulator, the thickness of the buried insulator in the direction perpendicular to the channel, and the distance from the side gate oxide to the buried insulator, respectively. L g , L side , L ov_xj , and L ov_side represent gate channel length, the length of the side-gate in the direction parallel to the channel, the overlapped length of the side-gate and S/D doping region shown in Figure 1a, and the side-channel width shown in Figure 1c, respectively. When L side and L ov_xj are increased, the width of the overlap region of the gate and the S/D region will also increase. The n + poly gate with a gate work function of 4.2 eV was applied. L g , L side , L ov_side and the recessed depth are 30 nm, 42 nm, 10 nm, and 100 nm, respectively. RFinFET is the modified S-FinFET with a structure in which the overlap region between the side-gate and the S/D region is removed [5]. Therefore, the Pi-FinFETs proposed in this paper can be divided into Pi-SFinFET and Pi-RFinFET depending on the presence or absence of the overlap region between the side-gate and the S/D region. Namely, in...

show abstract

Section: Resultsmentioning

confidence: 92%

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

et al. 2018

View full text Add to dashboard Cite

show abstract

“…Also, the off-currents, according to slope type of the PiFET, remained almost constant, because the electric field near the overlapped region of the gate and the drain region remains almost constant regardless of the slope type. Figure 4 shows the simulation results of the potential contour near the drain region for the PiFETs and the planar MOSFET, when V GS = 0 V and V DS = 1.6 V. The electrical characteristics, according to the dielectric constants of the buried insulator, could be explained by potential condensation and potential modulation phenomenon occurring near the drain region [14]. In the potential contours shown in Figure 4b-d, the potential modulation means that the starting point of the potential drop is shifted from an n − doped region to an n + doped region, near the drain region.…”

Section: Five Slopementioning

confidence: 99%

Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors

et al. 2018

View full text Add to dashboard Cite

In this paper, we extensively analyzed the drain-induced barrier lowering (DIBL) and leakage current characteristics of the proposed partial isolation field-effect transistor (PiFET) structure. We then compared the PiFET with the conventional planar metal-oxide semiconductor field-effect transistor (MOSFET) and silicon on insulator (SOI) structures, even though they have the same doping profile. Two major features of the PiFET are potential condensation and potential modulation by a buried insulator. The potential modulation near the drain region can control the electric field in the overlapped region of the drain and gate, because it causes a high gate-fringing field. Therefore, we suggest guidelines with respect to the optimal PiFET structure.

show abstract

“…On the other hand, PDW is mostly limited by the buried insulator of Pi-FinFET as shown in Figure 3b. Namely, the rather constant electric field in the buried insulator of Pi-FinFET induces a wider PDW near the drain region [10]. The dotted red ellipse in Figure 3b shows that the PDW is wider in the silicon layer compared to the conventional S-FinFET.…”

Section: Resultsmentioning

confidence: 92%

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

Lee¹,

kim²,

park³

et al. 2018

Preprint

View full text Add to dashboard Cite

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited 4 times lower Ioff than modified S-FinFET called RFinFET with more improved DIBL characteristics while minimizing Ion reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved DIBL and Ioff characteristics as gate channel length decreased.

show abstract

Gate induced drain leakage reduction with analysis of gate fringing field effect on high-κ/metal gate CMOS technology

Cited by 7 publications

References 29 publications

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors

Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors

Contact Info

Product

Resources

About