Gate input reconfiguration for combating soft errors in combinational circuits

A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits

“…Having got the soft error vulnerabilities of an individual gate, the soft error vulnerabilities of the whole circuit can be calculated by summing up the soft error vulnerabilities of each gate [22]- [25]. As presented in Eq.…”

“…To evaluate the soft error rates of combinational circuit, the drain area is usually taken as the sensitive area for transistors [22]- [26]. Here, we focus on the case where the drain areas are hit by ions.…”

Soft error mitigation through selection of noninvert implication paths

“…However, these techniques have to pay the price on circuit performance degradation, including area, power, and delay. Therefore, current efforts are mainly imposed on the reduction of the overhead, such as the techniques based on shadow gates [14], gate input reconfiguration [15], addition of functionally redundant wires (FRWs) [16], etc. In [14], a primary gate is protected by a shadow gate whose outputs are connected by a pair of diodes.…”

“…In [14], a primary gate is protected by a shadow gate whose outputs are connected by a pair of diodes. In [15], the fact that gate inputs and transistor positions have a profound impact on SER, is used to reconfigure the inputs of gates. The authors in [16] propose a logic-level soft error mitigation method with selective addition of functionally redundant wires (FRWs).…”

“…Moreover, unlike previous soft error mitigation methods, which operate at the circuit level, this method operates at the logic level. This technique can also be combined with the other techniques [14,15] to get better results.…”