Gate leakage mechanisms in strained Si devices

Abstract

This work investigates gate leakage mechanisms in advanced strained Si/ SiGe metal-oxide-semiconductor field-effect transistor ͑MOSFET͒ devices. The impact of virtual substrate Ge content, epitaxial material quality, epitaxial layer structure, and device processing on gate oxide leakage characteristics are analyzed in detail. In state of the art MOSFETs, gate oxides are only a few nanometers thick. In order to minimize power consumption, leakage currents through the gate must be controlled. However, modifications to the energy band structure, Ge diffusion due to high temperature processing, and Si/ SiGe material quality may all affect gate oxide leakage in strained Si devices. We show that at high oxide electric fields where gate leakage is dominated by Fowler-Nordheim tunneling, tensile strained Si MOSFETs exhibit lower leakage levels compared with bulk Si devices. This is a direct result of strain-induced splitting of the conduction band states. However, for device operating regimes at lower oxide electric fields Poole-Frenkel emissions contribute to strained Si gate leakage and increase with increasing virtual substrate Ge content. The emissions are shown to predominantly originate from surface roughness generating bulk oxide traps, opposed to Ge diffusion, and can be improved by introducing a high temperature anneal. Gate oxide interface trap density exhibits a dissimilar behavior and is highly sensitive to Ge atoms at the oxidizing surface, degrading with increasing thermal budget. Consequently advanced strained Si/ SiGe devices are inadvertently subject to a potential tradeoff between power consumption ͑gate leakage current͒ and device reliability ͑gate oxide interface quality͒.

Impact of mechanical stress on direct and trap-assisted gate leakage currents in p-type silicon metal-oxide-semiconductor capacitors

“…3͑b͒. 25 Therefore, both compressive and tensile stresses along ͓110͔ cause a decrease in the trap activation energy at P b0 and P b1 centers, ⌬ T ͑͒ Ͻ 0, 9,11,26 resulting in an increase in trap-assisted gate leakage current for both gate and substrate injections, as shown in Fig. 1͑b͒.…”

“…6 It has been reported that mechanical stress affects trap generation in metal-oxide-semiconductor ͑MOS͒ devices, 9,10 but less attention has been paid to mechanical stress-altered trap-assisted gate tunneling current. 11 In this work, we report for the first time the effects of uniaxial stress on trap-assisted gate tunneling current by using controlled applied mechanical stress and constant voltage stress ͑CVS͒.…”

On the dc and noise properties of the gate current in epitaxial Ge p-channel metal oxide semiconductor field effect transistors with TiN∕TaN∕HfO2∕SiO2 gate stack

“…12 A possible explanation is that the traps responsible for enhanced PF conduction in the device operative regimes are due to Ge out diffusion into the gate oxide. 3,7,8,13 On wafer gate current, low frequency noise measurements have been done by using a dedicated noise measurement system. 9 The gate current power spectral density ͑PSD͒ for both Ge pMOSFETs and reference Si pMOSFETs show a 1/ f ␥ behavior with ␥ nearly equal to 1.…”

Improved gate oxide integrity of strained Si n-channel metal oxide silicon field effect transistors using thin virtual substrates

“…Most studies of oxides in strained Si devices were entirely focused on the oxide/semiconductor interface quality ͑e.g., fast interface states͒ and the detrimental impact of Ge diffusion from the SiGe virtual substrate to the Si surface. 18 The impact of virtual substrate Ge composition, strained Si channel thickness, virtual substrate material quality, and thermal budget was examined. The paucity of comprehensive experimental data is unfortunate since the increased electron affinity of tensile strained Si compared to that of bulk Si theoretically leads to a reduction in tunneling currents.…”