Nonvolatile memory structures using Ge nanocrystals embedded in SiO2 have been characterized by room and low temperature current–voltage and capacitance–voltage measurements. The Ge nanocrystals have been fabricated by low pressure chemical vapor deposition process which is shown to be well suited for a real control of the tunnel oxide thickness. The deposition conditions allow a separate control of nc-Ge density and size. Using capacitance–voltage characterizations on nonvolatile memory structures, we have measured the charging and discharging kinetics of holes for tunnel oxides in the range 1.2–2.5 nm. Using current–voltage measurements and simulations, we have also shown that nc-Ge are at the origin of a tunnel-assisted current. Simulations have demonstrated that the hole’s charging effects strongly reduce the current density across the nonvolatile memory structure. Combined with a good control of nc-Ge properties, the use of Ge dots with large diameters (>10 nm) seems to be a promising way for p-type memory applications.

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This work investigates gate leakage mechanisms in advanced strained Si/ SiGe metal-oxide-semiconductor field-effect transistor ͑MOSFET͒ devices. The impact of virtual substrate Ge content, epitaxial material quality, epitaxial layer structure, and device processing on gate oxide leakage characteristics are analyzed in detail. In state of the art MOSFETs, gate oxides are only a few nanometers thick. In order to minimize power consumption, leakage currents through the gate must be controlled. However, modifications to the energy band structure, Ge diffusion due to high temperature processing, and Si/ SiGe material quality may all affect gate oxide leakage in strained Si devices. We show that at high oxide electric fields where gate leakage is dominated by Fowler-Nordheim tunneling, tensile strained Si MOSFETs exhibit lower leakage levels compared with bulk Si devices. This is a direct result of strain-induced splitting of the conduction band states. However, for device operating regimes at lower oxide electric fields Poole-Frenkel emissions contribute to strained Si gate leakage and increase with increasing virtual substrate Ge content. The emissions are shown to predominantly originate from surface roughness generating bulk oxide traps, opposed to Ge diffusion, and can be improved by introducing a high temperature anneal. Gate oxide interface trap density exhibits a dissimilar behavior and is highly sensitive to Ge atoms at the oxidizing surface, degrading with increasing thermal budget. Consequently advanced strained Si/ SiGe devices are inadvertently subject to a potential tradeoff between power consumption ͑gate leakage current͒ and device reliability ͑gate oxide interface quality͒.