Gate Level NBTI and Leakage Co-Optimization in Combinational Circuits with Input Vector Cycling

Pendyala, Shilpa; Islam, Sheikh Ariful; Katkoori, Srinivas

doi:10.1109/tetc.2018.2799739

Cited by 6 publications

(3 citation statements)

References 42 publications

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“…Dual threshold voltage assignment (DVth) is widely used for low-voltage low-power and low leakage power applications [27]. In dual Vth designs, higher Vth is assigned to the gates in non-critical paths for reducing the leakage power, and lower Vth is assigned to the gates in critical paths for improving performance/timing yield [27]. Implementing dual Vth technique is easy to fabricate by using an additional mask layer [27].…”

Section: Dual Threshold Voltage Assignment Techniquementioning

confidence: 99%

“…In dual Vth designs, higher Vth is assigned to the gates in non-critical paths for reducing the leakage power, and lower Vth is assigned to the gates in critical paths for improving performance/timing yield [27]. Implementing dual Vth technique is easy to fabricate by using an additional mask layer [27]. Here, we propose applying dual Vth assignment technique for reducing the impact of BTI on the circuit delay for improving the lifetime reliability.…”

Section: Dual Threshold Voltage Assignment Techniquementioning

confidence: 99%

“…There are several approaches presented for mitigating the impact of either PV [11] or aging [27]- [31] in combinational circuits. Due to the interdependencies between PV and aging [14], [29], the mitigation technique which ignores PV or aging effects results in non-optimized solutions.…”

Section: Introductionmentioning

confidence: 99%

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Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

et al. 2021

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In nano-scale CMOS technology, circuit reliability is a growing concern for complicated digital circuits due to manufacturing process variation and aging effects. In this paper, a statistical circuit optimization framework is presented to analyze and improve the lifetime reliability of digital circuits in the presence of process variation and aging degradation. The proposed framework takes advantage of a process variation-and aging-aware gate-level delay degradation model to characterize and evaluate the lifetime reliability of combinational circuits. A metric called Guardband-Aware Reliability (abbreviated as GAR) is proposed for a fair evaluation of the lifetime reliability of combinational circuits considering a guardband and timing yield specified by the designer. Then, using a criticality metric, a set of statistically critical gates is selected for being optimized in the optimization framework. As the improvement procedure, the dualthreshold voltage assignment technique is applied to the identified critical gates to enable the manufactured chip to improve the lifetime reliability in terms of low timing yield loss. Experimental results on ISCAS'85 and ISCAS'89 benchmark circuits show that our proposed framework increases the circuit reliability up to 9.93% for a 6-year lifetime imposing less than 6.9% timing yield loss.

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Section: Dual Threshold Voltage Assignment Techniquementioning

confidence: 99%

Section: Dual Threshold Voltage Assignment Techniquementioning

confidence: 99%

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Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

et al. 2021

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Lookup table‐based negative‐bias temperature instability effect and leakage power co‐optimization using genetic algorithm approach

Bhattacharjee

Sahu

Pradhan

2021

Circuit Theory & Apps

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SummaryAs a result of continuous scaling of transistors, negative bias temperature instability (NBTI) has become a serious reliability concern which causes the device to degrade over its lifetime. Similarly, leakage power also remains a key issue in deep submicron technologies. Both NBTI‐related delay degradation and standby time leakage power depend strongly on the circuit's input patterns. The input vector control (IVC) technique can be used for mitigating both NBTI‐related delay degradation and leakage power. However, the input vectors with the least NBTI‐induced degradation may not be the same ones with the least leakage power in any circuit; therefore, co‐optimization is needed to minimize leakage and NBTI‐induced degradation. In this paper, a genetic algorithm (GA)‐based approach is presented to co‐optimize both NBTI‐related performance degradation and also leakage power. We are also presenting a trade‐off analysis by giving different weightage to the NBTI effect and leakage power. Simulation results applied on ISCAS'85 benchmark circuits illustrate that on average our proposed technique saves up to 21.85% and 17.68% circuit performance degradation and the leakage power, respectively.

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A meta-heuristic search-based input vector control approach to co-optimize NBTI effect, PBTI effect, and leakage power simultaneously

Bhattacharjee

Das

Sahu

et al. 2023

Microelectronics Reliability

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Gate Level NBTI and Leakage Co-Optimization in Combinational Circuits with Input Vector Cycling

Cited by 6 publications

References 42 publications

Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

Lookup table‐based negative‐bias temperature instability effect and leakage power co‐optimization using genetic algorithm approach

A meta-heuristic search-based input vector control approach to co-optimize NBTI effect, PBTI effect, and leakage power simultaneously

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