Gate-level test generation for sequential circuits

Cheng, Kwang-Ting

doi:10.1145/238997.238999

Cited by 14 publications

(5 citation statements)

References 71 publications

(126 reference statements)

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“…Commercial gate-level sequential test generators either use topological analysis algorithms or are enhanced from a fault simulator or use mixed methods that combine topological analysis and simulation based methods [1], [2]. Test generation can also be modeled as a Boolean satisfiability (SAT) problem.…”

Section: A Related Workmentioning

confidence: 99%

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Improving the performance of automatic sequential test generation by targeting hard-to-test faults

Lingappan

Jha

2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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Automatic test pattern generation (ATPG) for sequential circuits usually involves search for a sequence of vectors to detect single stuck-at faults. The sequential search space is exponential in the memory elements and primary inputs. Existing sequential test generators are known to spend substantial amounts of run-time in searching for test sequences to detect hard-to-test faults. In this paper, we present a pre-process stage that precedes sequential test generation for each hard-to-test fault and prunes the sequential search space, which in turn reduces the test generation time for these faults. In this stage, the effects of different conditions imposed on the circuit for test generation are propagated as far as possible. This process requires only a single pass through the iterative array model of the given circuit. Using the pre-process stage along with a Boolean satisfiability (SAT) based sequential test generator, we show that the proposed approach is on an average 11.3X (maximum 25.2X) faster than an efficient gate-level sequential test generator for hard-to-test faults in ISCAS'89 benchmark circuits. The proposed pre-process stage is also applicable to sequential test generation at the register-transfer level (RTL) and improves the overall performance of an efficient sequential test generator at the RTL by 3.5X on average and a maximum of 4.6X for all faults.

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Section: A Related Workmentioning

confidence: 99%

“…Sequential ATPG usually involves search for a sequence of vectors to detect a single stuck-at fault in a sequential circuit [1], [2]. Due to the presence of memory elements, the controllability and observability of internal signals are, in general, much worse than those in a combinational circuit.…”

Section: Introductionmentioning

confidence: 99%

Improving the performance of automatic sequential test generation by targeting hard-to-test faults

Lingappan

Jha

2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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“…Sequential ATPG [4] is a search procedure that has similarities to symbolic simulation in that it is trying to produce a particular output value on a sequential circuit. Sequential ATPG algorithms work by either simulating forward from an initial state to the satisfying output, or proceeding from the output and justifying backwards to an initial state.…”

Section: Decision Proceduresmentioning

confidence: 99%

Reliable verification using symbolic simulation with scalar values

Wilson

Dill

2000

Proceedings of the 37th Conference on Design Automation - DAC '00

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This paper presents an algorithm for hardware verification that uses simulation and satisfiability checking techniques to determine the correctness of a symbolic test case on a circuit. The goal is to have coverage greater than that of random testing, but with the ease of use and predictability of directed testing. The user uses symbolic variables in simple directed tests to increase the input space that is explored. The algorithm, which is called quasi-symbolic simulation, simulates these tests using only scalar (0,1,X) values internally causing potentially conservative values to be generated at the outputs. Divide and conquer of the symbolic input space is used to resolve this conservativeness. In the best case, this method is as efficient as symbolic simulation using BDDs and, in the worst case, gives coverage and predictability at least as good as directed testing.

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“…Typical fault-oriented test generation techniques for gate-level sequential circuits [10] iteratively apply a test generation algorithm for combinational circuits using the iterative logic array (ILA) model of the circuit. Circuits of the size and complexity of pipelined microprocessors still exceed the capabilities of current gatelevel sequential test generation methods.…”

Section: Related Workmentioning

confidence: 99%

High-level test generation for design verification of pipelined microprocessors

Campenhout

Mudge

Hayes

1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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This paper addresses test generation for design verification of pipelined microprocessors. To handle the complexity of these designs, our algorithm integrates high-level treatment of the datapath with low-level treatment of the controller, and employs a novel "pipeframe" organization that exploits high-level knowledge about the operation of pipelines. We have implemented the proposed algorithm and used it to generate verification tests for design errors in a representative pipelined microprocessor.

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Gate-level test generation for sequential circuits

Cited by 14 publications

References 71 publications

Improving the performance of automatic sequential test generation by targeting hard-to-test faults

Improving the performance of automatic sequential test generation by targeting hard-to-test faults

Reliable verification using symbolic simulation with scalar values

High-level test generation for design verification of pipelined microprocessors

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