High-level test generation for design verification of pipelined microprocessors

Abstract

This paper addresses test generation for design verification of pipelined microprocessors. To handle the complexity of these designs, our algorithm integrates high-level treatment of the datapath with low-level treatment of the controller, and employs a novel "pipeframe" organization that exploits high-level knowledge about the operation of pipelines. We have implemented the proposed algorithm and used it to generate verification tests for design errors in a representative pipelined microprocessor.

Coverage metrics for functional validation of hardware designs

“…23 The major weakness of these metrics is that the fault models are motivated more by ease of definition and use than actual correspondence to design errors. Moreover, ease of measurement usually necessitates additional restrictions, such as the singlefault assumption 22 or the assumption that faults are not masked later in the simulation run.…”

Functional Test Compaction

“…For validation of pipelined processors, many FSM modelbased test generation techniques have been developed where an FSM model is used to generate a test suite for state, transition, or path coverage [2,37]. A significant bottleneck in these methods is the high complexity of FSM models, resulting in state explosion problem.…”

Test Generation Using Design and Property Decompositions

“…Finite state machines (FSM) have been widely used for representing the behavior of sequential systems and FSM coverage metrics can be used for effective verification. In FSM-based test generation, FSM coverage is used to generate test programs based on reachable states and state transitions [1][2][3][4]. Since complicated micro-architectural mechanisms in modern processor designs include interactions among many pipeline stages and buffers, the FSM-based approaches suffer from the state space explosion problem.…”