Gate-Lifted nMOS ESD Protection Device Triggered by a p-n-p in Series With a Diode

Lai, Da-Wei; Sque, S. J.; Peters, W.C.M.; Smedes, T.

doi:10.1109/ted.2019.2899457

Cited by 5 publications

(3 citation statements)

References 9 publications

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“…Therefore, an attempt was made to design a protection element that would increase the breakdown voltage and reduce the electric field value. Electrostatic discharge (ESD) [1][2][3][4][5][6][7] can occur because of excessive transient currents, which can be caused by the switching on and off of a power supply, the incomplete grounding of a machine, or human contact with an integrated circuit (IC) through human grounding (i.e., the Human Body Model). Notably, ESD can also irreversibly damage an IC.…”

Section: Introductionmentioning

confidence: 99%

Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components

Mai

Chen

et al. 2023

Electronics

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This study used a TSMC 0.18 µm 50 V process to build a high-voltage n-LDMOS structure. In the reference device, the number of floating poly (poly-2) turns was 7, and the width and spacing of each turn was 1 µm. The experiment was realized in three steps, i.e., fixing the number of laps by occupying the width of the structure, adjusting the width of each turn, and adjusting the distance between turns. The first step was fixed to occupy the width of the structure chart to adjust the number of turns. The number of turns increased from 7 to 9 and then decreased to 5 and 3 turns. The reduction in the number of turns resulted in a greater reduction in maximum electric field and an increase in breakdown voltage. A comparison of the 3-turn set with the reference set showed a 42% reduction in maximum electric field, from 4.17 × 103 to 2.46 × 103 (V/cm), and an increase in breakdown voltage (VBK) from 30.2 V to 35.84 V. The second step was to adjust the width of each turn from 1 to 1.4, 1.2, 0.8, and 0.6 µm. This increase in width reduced the maximum electric field, resulting in a greater increase in VBK. When the width was increased to 1.4 µm, the maximum field decreased from 1.95 × 103 V/cm to 1.4 × 103 V/cm and the VBK increased from 30.2 V to 85.6 V, an increase of 183%. The third step was to adjust the per-turn spacing of the reference group from 1 to 1.4, 1.2, 0.8, and 0.6 µm. When the spacing was reduced to 0.6 µm, the maximum electric field decreased by 33% from 1.95 × 103 to 1.32 × 103 V/cm and the VBK increased by 345% from 30.2 to 134.4 V.

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Section: Introductionmentioning

confidence: 99%

Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components

Mai

Chen

et al. 2023

Electronics

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“…There are several possible methods to improve the V h of the LVTSCR [10][11][12][13][14][15]. The most common solution is to expand the base region of the SCR's parasitic bipolar junction transistors (BJT) for decreasing the injection efficiency of their emitter-base junctions [10].…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, a gate-to-ground NMOS-triggered LVTSCR (GGSCR) was reported in [ 13 ], which increases the V h by leading the drain of the embedded NMOS to the anode, but it might cause the embedded NMOS to be damaged before the SCR conduction in a low current. Recently, the compound LVTSCR structures performing low V t1 as well as high V h were demonstrated in [ 14 , 15 ]. These compound structures are designed with high complexity and area requirements, thus limiting their application in advanced CMOS technology considering the design costs.…”

Section: Introductionmentioning

confidence: 99%

Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

et al. 2020

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Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

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Research on ESD Protection of Ultra-High Voltage nLDMOS Devices by Super-Junction Engineering in the Drain-Side Drift Region

Lan

Chen

et al. 2021

IEEE J. Electron Devices Soc.

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Electrostatic discharge (ESD) transient events can often damage semiconductor components. Therefore, the ultrahigh-voltage (UHV) circular n-channel lateral diffused metal-oxide-semiconductor transistor (nLDMOS) usually used in power electronics needs to have ESD self-protection capabilities. In this paper, the geometric parameters of 300-V and 200-V UHV circular nLDMOSs were modulated using different layouts at the drain side. The high-voltage p-well (HVPW) layer was used to form various super junctions (SJs) in the drift region. The modulations were classified as SJ length, SJ concentration-gradient thickness, HVPW ring-sector, and rotated SJ concentration gradient modulations in the drift region. Various HVPWs were used to produce several SJs in the drain drift region. According to the final measurement results, all modulation processes maintained the original physical characteristics of high breakdown voltage. Devices with the SJ length and SJ concentration-gradient thickness's modulations provided the best ESD robustness. The ESD testing value of the human-body model (HBM) will increase with the increase of the SJ length and SJ thickness modulations. The HBM value increased from the 1500 V reference to 4000V (increased by 166.66%).

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Gate-Lifted nMOS ESD Protection Device Triggered by a p-n-p in Series With a Diode

Cited by 5 publications

References 9 publications

Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components

Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components

Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

Research on ESD Protection of Ultra-High Voltage nLDMOS Devices by Super-Junction Engineering in the Drain-Side Drift Region

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