Gate oxide reliability of 4H-SiC V-groove trench MOSFET under various stress conditions

Modeling of interelectrode parasitic elements of V-groove SiC MOSFET

“…The absence of the depletion region in the drift layer also eliminates the parasitic resistance associated with the JFET region, which contributes to realize much lower onresistance than the VDMOSFET structure. The V-groove power MOSFET in [4] utilizes embedded p-layers to mitigate high electric field, which is mostly concentrated at the bottom of the gate terminal. In this section, through TCAD simulations, bias dependence of the parasitic components in the Vgroove power MOSFET is analyzed.…”

“…The dimensions and material properties are obtained according to the published article [4]. The dimension and doping concentration of the embedded p-layer, which are not described in [4], are determined referring to [10][11][12][13]. Current flows upwards, from the bottom (drain) to top (source), in the figure.…”

“…The vertical double-diffused MOSFET (VDMOSFET) structure is widely utilized in high power applications of SiC power MOSFETs. Other structures are also studied to sufficiently elicit the superior property of SiC materials [3,4]. An example is a V-groove trench structure with buried players [4].…”

“…Other structures are also studied to sufficiently elicit the superior property of SiC materials [3,4]. An example is a V-groove trench structure with buried players [4]. This structure is expected to improve the efficiency of power conversion while maintaining high breakdown voltage.…”

“…The V-groove structure utilizes high mobility facet and eliminates JFET region at which the on-resistance of regular DMOSFETs becomes high, thereby improving on-resistance of the SiC MOSFETs. In order to prevent from the oxide breakdown to occur, due to the concentration of electric field at the bottom of the trench structure, p-layers are buried in the n − epitaxial layer [4].…”