Gate oxide reliability projection to the sub-2 nm regime

Weir, B. E.; Alam, Muhammad Ashraful; Bude, J.; Silvėrman, P. J.; Ghetti, A.; Baumann, F.H.; Diodato, P.W.; Monroe, Don; Sorsch, T.; Timp, G.; Ma, Yi; Brown, M.M.; Hamad, Abdullah; Hwang, D.; Mason, P.

doi:10.1088/0268-1242/15/5/304

Cited by 77 publications

(26 citation statements)

References 18 publications

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“…The high carrier energy would appear to preclude AHI from taking place at lower voltages, especially at circuit operating voltages. An additional physical process involving minority ionization [39], [40] of holes in p-type anode material or lightly doped inverted n-type material was proposed that would allow hole injection at low voltages. This modification to the model and the experimental evidence that a critical hole fluence ( ) was required for oxide breakdown [17] substantiated the AHI model.…”

Section: Energy and Electron-induced Defect Generationmentioning

confidence: 99%

“…The holes could be injected through or over the oxide energy barrier. An important result from a detailed AHI model developed by Alam [50] predicted the voltage dependence of the voltage acceleration factor [the slope of the versus characteristic] observed by others [21], [40], [51] for ultrathin SiO films and will be discussed in more detail in Section III-B.…”

Section: Energy and Electron-induced Defect Generationmentioning

confidence: 99%

“…The thinner oxides (1.4-1.6 nm) appear to exhibit a larger voltage acceleration. It was later realized that the voltage acceleration parameter was a function of voltage not oxide thickness [40], [75]. Thinner oxides are tested at lower voltages than thicker oxides.…”

Section: B Voltage and Temperature Accelerationmentioning

confidence: 99%

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Ultrathin gate oxide reliability: physical models, statistics, and characterization

Suehle

2002

IEEE Trans. Electron Devices

145

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Abstract-The present understanding of wear-out and breakdown in ultrathin ( 5 0 nm) SiO 2 gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of defects required to cause breakdown and percolation theory will be used to describe the observed statistical failure distributions for ultrathin gate dielectric breakdown. Recent observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. Finally, the implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed.

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Section: Energy and Electron-induced Defect Generationmentioning

confidence: 99%

Section: Energy and Electron-induced Defect Generationmentioning

confidence: 99%

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Ultrathin gate oxide reliability: physical models, statistics, and characterization

Suehle

2002

IEEE Trans. Electron Devices

145

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“…It was therefore suggested that SBD would not cause device or circuit failure in many applications [146]. However, Pompl et al [194] and others [135], [138], [195], [196] later showed that SBD will cause a significant increase in the transistor-off current if the breakdown spot is in the drain region, which is increasingly likely in short-channel devices. This will be referred to as "device breakdown."…”

Section: B Device Breakdownmentioning

confidence: 99%

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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Abstract-The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 nm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO 2 -based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1% of these paths ultimately lead to destructive breakdown, and the microscopic nature of these defects is not known. The rate of defect generation decreases approximately exponentially with supply voltage, below a threshold voltage of about 5 V for hot electron-induced hydrogen release. However, the tunnel current also increases exponentially with decreasing oxide thickness, leading to a decreasing time-to-breakdown and a diminishing margin for reliability as device dimensions are scaled. Estimating the reliability of the dielectric requires an extrapolation from the measurement conditions (e.g., higher voltage) to operation conditions. Because of the diminished reliability margin, it has become imperative to try to reduce the error in this extrapolation.Long-term ( 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin ( 2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown. Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

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“…but ''will the circuit remain functioning after a ÔbreakdownÕ occurs?'' [1,2] To answer the latter it is essential to understand how the additional current through the FET gate oxide influences the behavior of the FET [3,4]. In the past we have addressed this issue in nFETs after hard [5] and soft breakdowns (SBD) [6].…”

Section: Introductionmentioning

confidence: 99%