Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Abstract

Abstract-The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 nm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO 2 -based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1% of these paths ultimately lead to destructive breakdown, and the microscopic nature of these defects is not known. The rate of defect generation decreases approximately exponentially with supply voltage, below a threshold voltage of about 5 V for hot electron-induced hydrogen release. However, the tunnel current also increases exponentially with decreasing oxide thickness, leading to a decreasing time-to-breakdown and a diminishing margin for reliability as device dimensions are scaled. Estimating the reliability of the dielectric requires an extrapolation from the measurement conditions (e.g., higher voltage) to operation conditions. Because of the diminished reliability margin, it has become imperative to try to reduce the error in this extrapolation.Long-term ( 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin ( 2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown. Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

Gate oxide evaluation under very fast transmission line pulse (VFTLP) CDM-type stress

“…Recently the Hydrogen Release Model, [16]- [17], [23]- [26], linked to the power law model, has also been reported as the physical breakdown mechanism. Nonetheless it was refuted by several authors [27]- [30]. A major endorsement of the power law model, however, came from the experimental work performed by Nicollian et al [31].…”

Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown

“…Extensive research has been conducted on the failure-causing physical phe-nomena, such as electromigration (EM) [22,2] and OBD [6]. The effect of OBD at the circuit level is a shift in the LOW and HIGH voltage values and eventually bit errors for CMOS devices [21,15,16].…”

Scalable methods for the analysis and optimization of gate oxide breakdown

“…At the device level, the mechanism and modeling of oxide breakdown have been studied for several decades, yielding a large number of publications, as surveyed in [1]. Various empirical and analytical models, including percolation models, have been proposed for this phenomenon.…”