Gate sizing to radiation harden combinational logic

Abstract

Abstract-A gate-level radiation hardening technique for costeffective reduction of the soft error failure rate in combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates that have the lowest logical masking probability to achieve costeffective tradeoffs between overhead and soft error failure rate reduction. The asymmetry in the logical masking probabilities at a gate is leveraged by decoupling the physical from the logical (Boolean) aspects of soft error susceptibility of the gate. Gates are hardened to single-event upsets (SEUs) with specified worst case characteristics in increasing order of their logical masking probability, thereby maximizing the reduction in the soft error failure rate for specified overhead costs (area, power, and delay). Gate sizing for radiation hardening uses a novel gate (transistor) sizing technique that is both efficient and accurate. A full set of experimental results for process technologies ranging from 180 to 70 nm demonstrates the cost-effective tradeoffs that can be achieved. On average, the proposed technique has a radiation hardening overhead of 38.3%, 27.1%, and 3.8% in area, power, and delay for worst case SEUs across the four process technologies.

Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

“…For both LET values, the circuits with higher drive strength (X2) have shown lower cross-section, as expected [34]. A common hardening technique is to upsize transistor dimensions to increase the nodal capacitance of the circuit and, consequently, the critical charge needed to observe a SET [34][35][36][37]. For 78 MeV•cm 2 /mg, the INV_X2, NAND_X1, and NAND_X2 provide the lowest SET cross-sections from all analyzed cells.…”

Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

“…here, Q coll is the charge deposited upon the strike of the particle, τ α and τ β are the collection and falling time constants, and they are selected to be 200 ps and 50 ps respectively [34,35]. Figure 6a shows the SEU current testbench that is created to test the selected FF while injecting the SEU current at the following cases:…”

“…It is exceedingly rare to get particles with LET values above ~30 MeV/cm 2 /mg [36], which is equivalent to ~650 fC. While many previous works [10,34,35] are reported for Qcoll = 100 fC and 150 fC only.…”

“…It is exceedingly rare to get particles with LET values above~30 MeV/cm 2 /mg [36], which is equivalent to~650 fC. While many previous works [10,34,35] are reported for Q coll = 100 fC and 150 fC only. Qcoll of 2.16 pC is equivalent to the highest LET of particles that can be found in space (~100 MeV/cm 2 /mg) according to (2), while L is the collection depth of ~2 µ m [10,34].…”

A DMR logic for mitigating the SET induced soft errors in combinational circuits

“…A layout hardening technique presented by Atkinson et al [4] exploits the pulse quenching effect to limit the pulse origination. At circuit-level, the usual approach is to increase the device size [5,6]. However, as the technology scales, the efficiency of these hardening techniques are reduced.…”