Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design

Abstract

Optimization algorithms have been successfully applied to the automatic design of analog integrated circuits. However, many of the existing solutions rely on expensive circuit simulations or use fully customized surrogate models for each particular circuit and technology. Therefore, the development of an easily adaptable low-cost and efficient tool that guarantees resiliency to variations of the resulting design, remains an open research area. In this work, we propose a computationally low-cost surrogate model for multi-objective optimization-based automated analog integrated circuit (IC) design. The surrogate has three main components: a set of Gaussian process regression models of the technology’s parameters, a physics-based model of the MOSFET device, and a set of equations of the performance metrics of the circuit under design. The surrogate model is inserted into two different state-of-the-art optimization algorithms to prove its flexibility. The efficacy of our surrogate is demonstrated through simulation validation across process corners in three different CMOS technologies, using three representative circuit building-blocks that are commonly encountered in mainstream analog/RF ICs. The proposed surrogate is 69 X to 470 X faster at evaluation compared with circuit simulations.

A Systematic Design Optimization Approach for Multiphysics MEMS Devices Based on Combined Computer Experiments and Gaussian Process Modelling

“…The design and analysis of computer experiments (DACE) based on GP models are now a popular choice for the development of metamodels, using deterministic computer simulations, in different fields and allow the design space exploration with minimum computational cost [32][33][34][35]. For MEMS devices, the DACE based design optimization, combined with the FEM based MEMS simulation tools and latest high computing machines, can greatly minimize the MEMS development cycle time and reduce the costs involved in the traditional iterative microfabrication runs for the realization of a fully functional MEMS device.…”

Sizing CMOS Amplifiers by PSO and MOL to Improve DC Operating Point Conditions

“…Therefore, to satisfy the objectives it is necessary that the widths and lengths: W4, W5, L4 and L5, remain around the values shown in Figure 12, since outside these ranges the circuit could not meet the target specifications. Some recent research has been done by applying regression techniques [46], and it can be combined to improve the sizing of MOS amplifiers to enhance important characteristics as slew rate [47].…”

Efficient Gaussian Process Calculations Using Chebyshev Nodes and Fast Fourier Transform

“…The utility of GP spans an array of tasks, encompassing regression [4][5][6], classification [7,8], and optimization [9,10]. These versatile models have found successful applications in diverse domains, including support for bike-sharing systems [11], computer vision [12], and even diesel engine optimization [13].…”