GCS: High-performance gate-level simulation with GPGPUs

Verification has grown to dominate the cost of electronic system design, consuming about 60% of design effort. Among several verification techniques, logic simulation remains the major verification technique. Speeding up logic simulation results in great savings and shorter time-to-market. We parallelize logic simulation using Graphics Processing Units (GPUs). In the past, GPUs were special-purpose application accelerators, suitable only for conventional graphics applications. The new generations of GPU architecture provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power of traditional GPUs. We develop a parallel cycle-based logic simulation algorithm that uses And Inverter Graphs (AIGs) as design representations. AIGs have proven to be an effective representation for various design automation applications, and we obtain similar benefits for speeding up logic simulation. We develop two clustering algorithms that partition the gates in the designs into independent blocks. Our algorithms exploit the massively parallel GPU architecture featuring thousands of concurrent threads, fast memory, and memory coalescing for optimizations. We demonstrate up-to 5x and 21x speedups on several benchmarks using our simulation system with the first and second clustering algorithms, respectively. Our work ultimately results in significant reduction in the overall design cycle.

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“…Our CBS algorithm is most similar to the work by Chatterjee et al [9]. However, there are several differences.…”

Section: Related Worksupporting

confidence: 59%

“…We fix the number of blocks in our second clustering algorithm in order to maximize parallel thread execution. We encode variables in order to better utilize shared memory and we explicitly use memory coalescing, whereas these are not used in [9].…”

Section: Related Workmentioning

confidence: 99%

Speeding Up Cycle Based Logic Simulation Using Graphics Processing Units

Şen

Akşanlı

Bozkurt

2011

Int J Parallel Prog

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“…Very recently (in particular, subsequent to the conference versions [10,19] of this paper), other researchers have also started looking into the possibility of accelerating EDA tasks using GPUs [15,23]. However, these attempts have been directed towards fault-simulation and gate-level simulation.…”

Section: Related Workmentioning

confidence: 95%

GPU-based Acceleration of System-level Design Tasks

Bordoloi

Chakraborty²

2010

Int J Parallel Prog

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Many system-level design tasks (e.g., high-level timing analysis, hardware/software partitioning and design space exploration) involve computational kernels that are intractable (usually NP-hard). As a result, they involve high running times even for mid-sized problems. In this paper we explore the possibility of using commodity graphics processing units (GPUs) to accelerate such tasks that commonly arise in the electronic design automation (EDA) domain. We demonstrate this idea via two detailed case studies. The first explores the possibility of using GPUs to speedup standard schedulability analysis problems. The second proposes a GPU-based engine for a general hardware/software design space exploration problem. Not only do these problems commonly arise in the embedded systems domain, their computational kernels turn out to be variants of a combinatorial optimization problem-viz., the knapsack problem-that lies at the heart of several EDA applications. Experimental results show that our GPU-based implementations offer very attractive speedups for the computational kernels (up to 100×), and speedups of up to 17× for the full problem. In contrast to ASIC/FPGA-based accelerators-given that even low-end desktop and notebook computers are now equipped with GPUs-our solution involves no extra hardware cost. Although recent research has shown the benefits of using GPUs for a variety of non-graphics applications (e.g., in databases and bioinformatics), harnessing the parallelism of GPUs to accelerate problems from the EDA domain has not been sufficiently explored so far. We believe that our results and the generality of the core U. D. Bordoloi (B) Centre Équation-2, problem that we address will motivate researchers from this community to explore the possibility of using GPUs for a wider variety of problems from the EDA domain.

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“…While gate-and RTLlevel simulators can co-simulate both software and hardware, their runtimes are orders of magnitude slower than real-time [7]. Cycle-accurate architecture-level simulators like Wattch [4] suffer from the same problem.…”

Section: Introductionmentioning

confidence: 94%

“…In VarEMU, a dynamic reliability management is implemented which automatically adjusts the supply voltage based on the delay reported by Equation (7). In this experiment, we use the aging model as in Section 3.3.…”

Section: Case Study: Dynamic Reliability Managementmentioning

confidence: 99%

VarEMU: An emulation testbed for variability-aware software

Wanner

Elmalaki

Lai

et al. 2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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Modern integrated circuits, fabricated in nanometer technologies, suffer from significant power/performance variation across-chip, chip-to-chip and over time due to aging and ambient fluctuations. Furthermore, several existing and emerging reliability loss mechanisms have caused increased transient, intermittent and permanent failure rates. While this variability has been typically addressed by process, device and circuit designers, there has been a recent push towards sensing and adapting to variability in the various layers of software. Current hardware platforms, however, typically lack variability sensing capabilities. Even if sensing capabilities were available, evaluating variability-aware software techniques across a significant number of hardware samples would prove exceedingly costly and time consuming.We introduce VarEMU, an extension to the QEMU virtual machine monitor that serves as a framework for the evaluation of variability-aware software techniques. VarEMU provides users with the means to emulate variations in power consumption and in fault characteristics and to sense and adapt to these variations in software. Through the use (and dynamic change) of parameters in a power model, users can create virtual machines that feature both static and dynamic variations in power consumption. Faults may be injected before or after, or completely replace the execution of any instruction. Power consumption and susceptibility to faults are also subject to dynamic change according to an aging model. A software stack for VarEMU features precise control over faults and provides virtual energy monitors to the operating system and processes. This allows users to precisely quantify and evaluate the effects of variations on individual applications. We show how VarEMU tracks energy consumption according to variation-aware power and aging models and give examples of how it may be used to quantify how faults in instruction execution affect applications.

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GCS: High-performance gate-level simulation with GPGPUs

Cited by 33 publications

References 12 publications

Speeding Up Cycle Based Logic Simulation Using Graphics Processing Units

Speeding Up Cycle Based Logic Simulation Using Graphics Processing Units

GPU-based Acceleration of System-level Design Tasks

VarEMU: An emulation testbed for variability-aware software

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