Ge effects on silicidation

Besser, Paul R.; King, Paul L.; Paton, E.; Robie, Stephen B.

doi:10.1016/j.mee.2005.07.044

Cited by 13 publications

(4 citation statements)

References 6 publications

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“…Ge is introduced to the active regions by selective epitaxial growth, in which the Ge replaces Si substitutionally. Although additions of Ge on the order of 20-30% are common, it is difficult to form a low resistance phase in the presence of Ge [4][5][6][7]. CoSi 2 has difficulty forming on Si-Ge substrates [6,[8][9][10], while Ni or NiPt do form a low resistance phase that is much more sensitive to both chemical attack and degradation upon annealing.…”

Section: Challenges For the Silicide Modulementioning

confidence: 99%

“…While the process window for Ni/SiGe is smaller than that for Ni/Si, this window is not affected to the point where it becomes impracticable. However, NiSi implementation on silicon-on-insulator (SOI) substrates has been influenced by morphological stability and other issues related to integration [6][7][16][17][18]. Understanding the formation sequence and its dependence on process parameters such as dopant concentration, substrate type, substrate preparation, and annealing conditions is important to build a process that is reliable and reproducible.…”

Section: Improvements To Nisi Morphological Stabilitymentioning

confidence: 99%

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Silicides for 22nm and Beyond

et al. 2008

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Silicide engineering for high-performance CMOS logic devices is challenged by aggressive scaling of critical dimensions, new high-performance elements, and requirements of morphological stability. While NiSi can satisfy many of the integration challenges, incorporating Pt forms a more robust [NixPt(1-x)]Si and improves morphological stability. In light of the challenges created by performance enablers, we review our latest results indicating whether a replacement for NiPt(1-x)Si is needed and highlight our investigations into alternative silicide materials such as Er, Yb, and Ir. We also discuss the architecture and performance needs beyond 32nm technology.

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Section: Challenges For the Silicide Modulementioning

confidence: 99%

Section: Improvements To Nisi Morphological Stabilitymentioning

confidence: 99%

Silicides for 22nm and Beyond

et al. 2008

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“…The enhanced device performance has been attributed to the sub-band structure modulation due to the compressed strain in the channel region. However, it is usually difficult to fabricate high-quality nickel germanosilicide (NiSiGe) on top of the SiGe/Si junction as the agglomeration of the NiSiGe film results in a rough interface of nickel silicide (NiSi) [2][3][4]. These interface defects generate high generation-recombination junction leakage and large sheet resistance of the NiSi film, resulting in junction and device performance degradation.…”

Section: Introductionmentioning

confidence: 99%

Impact of various silicide techniques on SiGe source–drain series resistance and mobility of pMOSFETs

Chang

et al. 2013

Semicond. Sci. Technol.

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A comparative experimental study of series resistance and hole mobility of pMOSFETs with silicon germanium (SiGe) junctions under various silicide techniques is carried out. It is found that using an additional germanium pre-amorphous implant process in the nickel silicide (NiSi) techniques does not affect the hole mobility. However, it increases the source/drain series resistance. On the other hand, an additional silicon capping layer process in the NiSi techniques not only improves the hole mobility, but also reduces the series resistance dramatically. Various MOSFET characterizations from the silicide techniques are mainly due to the differences in the NiSi/SiGe interface structures in those devices.

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“…However, it is difficult to fabricate high quality nickel germano-silicide on the top of the SiGe/Si junction due to the agglomeration of the NiSiGe film [1][2][3] and Ni penetrating into the junction region. This silicide damage usually leads to the high junction leakage [2], which could be one significant contributor to the off-state leakage current of sub-65nm pMOSFETs [4].…”

Section: Introductionmentioning

confidence: 99%

The influence of silicide technique on the device performance for deep sub-micro pMOSFETs

Liao

Chang

et al. 2012

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology

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We investigate the junction leakage current and device performance for 45nm SiGe/Si pMOSFETs using various silicide technology. It is found that with the conventional Ni silicide method, the leakage current of a SiGe/Si junction is large and attributed to band-to-band tunneling and the generation-recombination process. The two leakage contributors can be suppressed quite effectively when a Si cap layer is added in the Ni silicide method. In addition, Si-cap methods show the best current voltage characteristic for MOSFETs. The characteristic improvement could be associated with the suppression of the agglomeration of the Ni germano-silicide film. Our results show the novel Ni silicide method using a Si cap is the most promising choice for SiGe junctions in advanced technology.

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Ge effects on silicidation

Cited by 13 publications

References 6 publications

Silicides for 22nm and Beyond

Silicides for 22nm and Beyond

Impact of various silicide techniques on SiGe source–drain series resistance and mobility of pMOSFETs

The influence of silicide technique on the device performance for deep sub-micro pMOSFETs

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