Ge ion implantation in Si for the fabrication of Si/GexSi1-x heterojunction transistors

Lombardo, S.; Raineri, V.; Via, F. La; Iacona, Fabio; Campisano, S. U.; Pinto, A.; Ward, Peter

doi:10.1016/s0254-0584(96)01793-2

Cited by 6 publications

(7 citation statements)

References 15 publications

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“…Successful epitaxial silicon growth on a few-angstroms-thick ALD of BeO is reported . Ge ion implantation into the 45-nm-long W II region of the 10-nm-thick SOI would yield a uniform SiGe base. − A multiple masking and patterning of the W II region for increasing doses of Ge ion implantation would result in a small stepwise graded SiGe W II region (from 0 to 0.5 Ge in SOI). This small stepwise graded Ge in silicon would closely resemble the linearly graded SiGe because the length of the base is very small.…”

Section: Proposed Process Flow For the Fabrication Of The 3scp Slhbt ...mentioning

confidence: 99%

“…There have been reports on how to fabricate charged plasma devices and on techniques and processes for performing Ge ion implantation to create the SiGe region. − A probable process flow for the novel 3SCP SLBT on SiGe-OI is reported . A potential suitable process flow for our novel 3SCP SLHBT on the SOI device structure is proposed in section .…”

Section: Introductionmentioning

confidence: 99%

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Comparative Study of Different Configurations in Triple-Sided Charged Plasma Symmetric Lateral Heterojunction Bipolar Transistors on SOI

Devi

Srivastava

2019

ACS Appl. Electron. Mater.

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A comparative simulation study of triple-sided charged plasma symmetric lateral heterojunction bipolar transistors (3SCP SLHBTs) on SOI is performed for the first time. A 3SCP SLHBT has all the advantages that a conventional charge plasma (cCP) lateral bipolar on SOI has, namely, overcoming the issue related to the thermal budget along with improvements in current gain and speed. Our new design along with the heterojunction configuration is able to further improve upon the performance of cCP design by inducing carriers from the bottom, side, and top with respect to cCP design where the carrier concentration is low toward the bottom region of the active device layer. Our novel 3SCP SLHBT design shows huge improvements in current gain, f T , and f max by almost 1092, 80.6, and 51.6% respectively with repsect to cCP SLHBT design. In this article, we carried out a systematic study of the heterojunction bipolar structure of the 3SCP device design with three different HBT configurations and presented a comparative study of their performance. The different 3SCP SLHBT configurations studied here as emitter-base-collector are Si-0.3Ge-Si, Si-linearly graded SiGe-Si, and Si-Ge-Si, respectively. We are able to achieve the same collector current but with a lower V BE by ∼320 mV when a device having a Si-linearly graded SiGe-Si configuration is replaced with a device having a Si-Ge-Si configuration. We are able to achieve and demonstrate this novel HBT device with the best optimal performance parameters for the Si-0.3Ge-Si configuration. This device shows a current gain of 8.4 × 10 5 , with f T = 428.87 GHz and f max = 2.38 THz. We are also able to successively demonstrate the symmetric complementary 3SCP SLHBT inverter using the Si-0.3Ge-Si configuration having optimal digital circuit performance parameters. The inverter has a switching voltage (V M ) of 0.505 V, a low noise margin (NM L ) of 0.47 V, and a high noise margin (NM H ) of 0.45 V at 1 V.

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Section: Proposed Process Flow For the Fabrication Of The 3scp Slhbt ...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Comparative Study of Different Configurations in Triple-Sided Charged Plasma Symmetric Lateral Heterojunction Bipolar Transistors on SOI

Devi

Srivastava

2019

ACS Appl. Electron. Mater.

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“…16i. Germanium can now be implanted [22][23][24][25] through this window to convert silicon in the base region to SiGe. Ge implantation can be performed at an energy of 130 keV with fluences of 1, 2 or 3 Â 10 16 cm À2 according to the reported works in the literature [22].…”

Section: Proposed Fabrication Proceduresmentioning

confidence: 99%

“…Germanium can now be implanted [22][23][24][25] through this window to convert silicon in the base region to SiGe. Ge implantation can be performed at an energy of 130 keV with fluences of 1, 2 or 3 Â 10 16 cm À2 according to the reported works in the literature [22]. To recrystallise the implanted SiGe layer, a rapid thermal annealing (RTA) needs to be performed at 10001C for about 10 s. This process is to ensure complete recrystallisation of the SiGe amorphous layer [22].…”

Section: Proposed Fabrication Proceduresmentioning

confidence: 99%

“…Ge implantation can be performed at an energy of 130 keV with fluences of 1, 2 or 3 Â 10 16 cm À2 according to the reported works in the literature [22]. To recrystallise the implanted SiGe layer, a rapid thermal annealing (RTA) needs to be performed at 10001C for about 10 s. This process is to ensure complete recrystallisation of the SiGe amorphous layer [22]. After converting silicon in the base region to SiGe, we then deposit n + -poly and then the wafer is once again planarised using CMP, leaving n + -poly in the place where the nitride film was present earlier as shown in Fig.…”

Section: Proposed Fabrication Proceduresmentioning

confidence: 99%

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Realising wide bandgap P-SiC-emitter lateral heterojunction bipolar transistors with low collector–emitter offset voltage and high current gain: a novel proposal using numerical simulation

Kumar

Reddy

2004

IEE Proc., Circuits Devices Syst.

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The authors report a novel method to reduce the collector-emitter offset voltage of the wide bandgap SiC-P-emitter lateral HBTs using a dual-bandgap emitter. In their approach, the collector-emitter offset voltage V CE(offset) is reduced drastically by eliminating the built-in potential difference between the emitter-base (EB) and collector-base (CB) junctions by using a SiC-on-Si P-emitter. It is demonstrated that the proposed dual-bandgap P-emitter HBT, together with the SiGe base and Schottky collector, not only has a very low V CE(offset) but also exhibits high current gain, reduced Kirk effect, excellent transient response and high cutoff frequency. The performance of the proposed device is evaluated in detail using two-dimensional device simulation, and a possible BiCMOS compatible fabrication procedure is also suggested.

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Epitaxial Ge-rich silicon layers after dry oxidation of Ge implanted silicon

Baghizadeh

Lotfi

Agha-Aligol

2019

Vacuum

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Ge ion implantation in Si for the fabrication of Si/GexSi1-x heterojunction transistors

Cited by 6 publications

References 15 publications

Comparative Study of Different Configurations in Triple-Sided Charged Plasma Symmetric Lateral Heterojunction Bipolar Transistors on SOI

Comparative Study of Different Configurations in Triple-Sided Charged Plasma Symmetric Lateral Heterojunction Bipolar Transistors on SOI

Realising wide bandgap P-SiC-emitter lateral heterojunction bipolar transistors with low collector–emitter offset voltage and high current gain: a novel proposal using numerical simulation

Epitaxial Ge-rich silicon layers after dry oxidation of Ge implanted silicon

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