Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms

Abstract

The rapid expansion of online-based services requires novel energy and performance efficient architectures to meet power and latency constraints. Fast architectural exploration has become a key enabler in the proposal of architectural innovation. In this paper, we present gem5-X, a gem5-based system level simulation framework, and a methodology to optimize many-core systems for performance and power. As real-life case studies of many-core server workloads, we use real-time video transcoding and image classification using convolutional neural networks (CNNs). Gem5-X allows us to identify bottlenecks and evaluate the potential benefits of architectural extensions such as in-cache computing and 3D stacked High Bandwidth Memory. For real-time video transcoding, we achieve 15% speed-up using in-order cores with in-cache computing when compared to a baseline in-order system and 76% energy savings when compared to an Out-of-Order system. When using HBM, we further accelerate real-time transcoding and CNNs by up to 7% and 8% respectively.

Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures

“…We use gem5-X 1 [28], an open source, validated and extended version of cycle-accurate gem5 [29] architectural simulator, which exhibits a validation error of up to 4% when simulating the ARMv8 64-bit cores of the JUNO platform [41]. ARM full-system (FS) simulation mode is used with an Ubuntu 16.04 OS, as all our case study applications require various OS multi-threading support.…”

“…Using this methodology we propose an optimized architecture based on 3D-stacked high bandwidth memory (HBM2) [27] alongside energy efficient ARMv8 64-bit compute cores. We use the gem5-X [28] architectural simulator, an open source, validated and enhanced version of gem5 [29], with HBM2 memory model. Three widely used state-of-the-art NGS applications namely, Bowtie2 [20], BWA-MEM [21] and HISAT2 [22] with different search strategies are used as case study applications for performance and energy optimization.…”

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

“…The Darknet framework and the gem5 architectural simulator [28], together with gem5-X [29] (which allowed to reduce the usual 10% error margin provided by gem5 to less than 4%), were used to evaluate the performance of the modified ARMv8 architecture. Darknet was set to operate as a trimmed version of the YoloV3 XNOR-Net CNN, and gem5 was configured to emulate the ARMv8 Cortex-A53 with and without the devised BDPE.…”

“…For the energy efficiency and power assessment of the proposed architecture, 28 nm FD-SOI power models for ARMv8 in-order cores were used, as proposed by [29] and [30]. The power models include active core power, Wait-For-Memory (WFM) power, and the static core power.…”

Challenges in Deeply Heterogeneous High Performance Systems

“…Furthermore, to assess the impact of reliability and thermal issues on the overall system architecture, we will also rely on simulation, which will be possible thanks to the recent gem5-X framework developed by EPFL. In RECIPE, gem5-X [31] will be equipped with both thermal and reliability simulation to evaluate the impact of architectural choices and resource management strategies in short and long term reliability. We will investigate stateof-the-art techniques in fault prediction technologies [32].…”