General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs

El-Chammas, Manar; Murmann, Boris

doi:10.1109/tcsi.2009.2015206

Cited by 88 publications

(25 citation statements)

References 12 publications

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“…The sampling timing is under control of four-phase differential clocks generated by the phase regulator, as shown in Figure 1. For a 6-bit resolution with an input frequency of 10 GHz, the standard deviation of the timing mismatch is required to be less than 0.2 ps, which corresponds to 0.36 degree [20][21][22]. An interpolator-based phase regulator is employed in the clock path to calibrate the timing mismatch in the analog domain, thus large area cost and complicated algorithm in digital calibration are avoided.…”

Section: Interpolator-based Phase Regulatormentioning

confidence: 99%

A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

Ding

Zheng

et al. 2019

Electronics

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This paper presents a 20 GS/s four-channel time-interleaved sample-and-hold amplifier (SHA), which aims to improve the harmonic distortion performance, eliminate the common-mode voltage fall in track-to-hold transition, and solve the difficulty of timing mismatch calibration among different sampling channels. In data path, the harmonic distortion of the track-hold switch is optimized by introducing a distortion-improving resistor into the switched emitter follower. The common-mode voltage fall is eliminated by an inserted delay-regulating resistor. Additionally, broadband data buffers are utilized to further guarantee a wide bandwidth. In clock path, an interpolator-based phase regulator in analog domain is implemented to calibrate the timing mismatch, hence avoiding the large area cost and complicated algorithm in the digital domain. Fabricated in a 0.18 μm SiGe BiCMOS process, the experimental results show that the SHA achieves a bandwidth of 16 GHz and a total harmonic distortion of −39.6 to approximately −51.8 dB with a −3 dBm input. By applying the proposed sampling phase regulator, the timing mismatch can be optimized to satisfy the requirement of 6-bit resolution at a 4 × 5 GS/s sampling rate. The proposed SHA shows prominent performance on both bandwidth and linearity, which makes it suitable for ultra-high-speed communication networks.

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Section: Interpolator-based Phase Regulatormentioning

confidence: 99%

A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

Ding

Zheng

et al. 2019

Electronics

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“…The calibration of timing skews in TI-ADCs is more complicated than offset and gain mismatch calibration. Many timing-skew calibration techniques have been proposed in theory, and have also been implemented on-chip or off-chip [16,29,59,60,66,67]. The key design considerations related to the clock signal generation for TI-ADCs are discussed in [65].…”

Section: Channel Timing Mismatch (Timing Skews)mentioning

confidence: 99%

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Zahrai

Onabajo

2018

JLPEA

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This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6-8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.

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“…The first term on the right-hand side is simply a time-shifted copy of the second, representing the effect of sampling with a timing mismatch of . Assuming rad, we expand the first term, obtaining (28) The second term arises from the derivative of the signal, but unlike the third term, it has not experienced frequency translation. Hiding behind the main component, this term has evidently not been considered in prior work because it is indistinguishable from the main signal for a sinusoidal input.…”

Section: Does Not Reveal Another Corruption Mechanismmentioning

confidence: 99%

“…Hiding behind the main component, this term has evidently not been considered in prior work because it is indistinguishable from the main signal for a sinusoidal input. The equal amplitudes of the second and third terms in (28) suggest that neglecting the second term underestimates the corruption by 3 dB.…”

Section: Does Not Reveal Another Corruption Mechanismmentioning

confidence: 99%

Design Considerations for Interleaved ADCs

Razavi

2013

IEEE J. Solid-State Circuits

264

136

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Interleaving can relax the power-speed tradeoffs of analog-to-digital converters and reduce their metastability error rate while increasing the input capacitance. This paper quantifies the benefits and derives an upper bound on the performance by considering noise and slewing requirements of the circuit driving the system. A frequency-domain analysis of interleaved converters is also presented that sheds light on the corruption mechanisms due to interchannel mismatches. A background timing mismatch calibration technique is proposed and experimentally shown to reduce the image to dB for input frequencies exceeding 500 MHz. Index Terms-Background calibration, flash analog-to-digital converters (ADCs), figure of merit, image, interleaving mismatches, low-power ADCs, pipelined ADCs, SAR ADCs, timing mismatch.

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General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs

Cited by 88 publications

References 12 publications

A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Design Considerations for Interleaved ADCs

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