Generating Target Graph Couplings for QAOA from Native Quantum Hardware Couplings

Rajakumar, Joel; Moondra, Jai; Gard, Bryan T.; Gupta, Ruta; Herold, Creston

doi:10.48550/arxiv.2011.08165

Cited by 2 publications

(3 citation statements)

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“…In addition, there are methods to overcome the measurement count limitations. One approach is to significantly increase hardware connectivity or modify the gate set, for example, using ion-trap quantum computers with globally-entangling Mølmer-Sørensen gates [60] or Rydberg atoms that naturally enforce constraints in some instances of QAOA [61]. Another approach is to modify the QAOA ansatz.…”

Section: Discussionmentioning

confidence: 99%

Scaling Quantum Approximate Optimization on Near-term Hardware

Lotshaw,

Nguyen,

Santana

et al. 2022

Preprint

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The quantum approximate optimization algorithm (QAOA) is an approach for near-term quantum computers to potentially demonstrate computational advantage in solving combinatorial optimization problems. However, the viability of the QAOA depends on how its performance and resource requirements scale with problem size and complexity for realistic hardware implementations. Here, we quantify scaling of the expected resource requirements by synthesizing optimized circuits for hardware architectures with varying levels of connectivity. Assuming noisy gate operations, we estimate the number of measurements needed to sample the output of the idealized QAOA circuit with high probability. We show the number of measurements, and hence total time to solution, grows exponentially in problem size and problem graph degree as well as depth of the QAOA ansatz, gate infidelities, and inverse hardware graph degree. These problems may be alleviated by increasing hardware connectivity or by recently proposed modifications to the QAOA that achieve higher performance with fewer circuit layers.

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Section: Discussionmentioning

confidence: 99%

Scaling Quantum Approximate Optimization on Near-term Hardware

Lotshaw,

Nguyen,

Santana

et al. 2022

Preprint

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“…Our targeted physical ion trap testbed and its control scheme have been modified for domain-specific computations based on global operations [20], so we cannot execute our benchmark circuits on the physical testbed itself. However, we can verify correct output of generated code by executing our operations in the simulator already included in the control software, originally used to aid in calibration.…”

Section: Evaluation a System Configurationmentioning

confidence: 99%

“…Lu et al [30] discuss a scalable scheme for implementing a global multi-qubit entangling gate which can potentially lead to exponential speedups as compared to a circuit decomposition involving single-and two-qubit entangling gates. The GTRI testbed is currently configured for specific multi-qubit global entangling operations [20], but we have not considered them in this work.…”

Section: Related Workmentioning

confidence: 99%

Enabling a Programming Environment for an Experimental Ion Trap Quantum Testbed

Adams¹,

Pinto²,

Young³

et al. 2021

Preprint

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Ion trap quantum hardware promises to provide a computational advantage over classical computing for specific problem spaces while also providing an alternative hardware implementation path to cryogenic quantum systems as typified by IBM's quantum hardware. However, programming ion trap systems currently requires both strategies to mitigate high levels of noise and also tools to ease the challenge of programming these systems with pulse-or gate-level operations.This work focuses on improving the state-of-the-art for quantum programming of ion trap testbeds through the use of a quantum language specification, QCOR, and by demonstrating multi-level optimizations at the language, intermediate representation, and hardware backend levels. We implement a new QCOR/XACC backend to target a general ion trap testbed and then demonstrate the usage of multi-level optimizations to improve circuit fidelity and to reduce gate count. These techniques include the usage of a backend-specific numerical optimizer and physical gate optimizations to minimize the number of native instructions sent to the hardware. We evaluate our compiler backend using several QCOR benchmark programs, finding that on present testbed hardware, our compiler backend maintains the number of two-qubit native operations but decreases the number of single-qubit native operations by 1.54 times compared to the previous compiler regime. For projected testbed hardware upgrades, our compiler sees a reduction in two-qubit native operations by 2.40 times and one-qubit native operations by 6.13 times.

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Generating Target Graph Couplings for QAOA from Native Quantum Hardware Couplings

Cited by 2 publications

References 0 publications

Scaling Quantum Approximate Optimization on Near-term Hardware

Scaling Quantum Approximate Optimization on Near-term Hardware

Enabling a Programming Environment for an Experimental Ion Trap Quantum Testbed

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