Generator based approach for analog circuit and layout design and optimization

Graupner, Achim; Jancke, Roland; Wittmann, R.

doi:10.1109/date.2011.5763267

Cited by 14 publications

(13 citation statements)

References 5 publications

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“…Such structures can be more naturally addressed with PCells -as SWARM's governing modules do. While PCells (i.e., procedural generators) can be implemented to automate complex analog blocks in full-custom quality [7], covering sufficient layout variability requires an immense development and maintenance overhead since resorting to fixedheight standard cell approaches as in [8] is not practicable for analog design. This is where the unique self-organization aspect of SWARM fills the gap to combine the quality of bottomup automation with the flexibility of top-down automation.…”

Section: Examples and Resultsmentioning

confidence: 99%

Analog layout automation via self-organization: Enhancing the novel SWARM approach

Marolt

Scheible

Jerke

et al. 2016

2016 IEEE 7th Latin American Symposium on Circuits &Amp; Systems (LASCAS)

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This paper enhances SWARM, a novel deterministic analog layout automation approach based on the idea of cellular automata. SWARM implements a decentralized interaction model in which responsive layout modules, covering basic circuit types, autonomously move, rotate and deform themselves to let constraint-compliant, compact layout solutions emerge from a synergetic flow of self-organization. With the ability to consider design constraints both implicitly and explicitly, SWARM joins the layout quality of procedural generators with the flexibility of optimization algorithms, combining these two kinds of automation into a "bottom-up meets top-down" flow. The new enhancements are demonstrated in an OTA example, depicting the power of SWARM and its enormous potential for future developments.

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Section: Examples and Resultsmentioning

confidence: 99%

Analog layout automation via self-organization: Enhancing the novel SWARM approach

Marolt

Scheible

Jerke

et al. 2016

2016 IEEE 7th Latin American Symposium on Circuits &Amp; Systems (LASCAS)

View full text Add to dashboard Cite

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“…2) Template-Based Approach: In [15], a generator approach is proposed. A set of basic analog building cells, like differential pair and current mirror, is implemented in a scalable and technology independent manner using generic model approach.…”

Section: ) Analytical Equation/linearized Equivalent Model-based Appmentioning

confidence: 99%

“…In the literature, numerical optimization algorithms are intensively employed in the automation procedure of technology migration and design reuse for topology synthesis, device resize, and biasing to meet all the design specs [2]- [7], [15], [17]- [22]. However, there still exist the following incommodities.…”

mentioning

confidence: 99%

Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework

Qian

Zhou

et al. 2015

IEEE Trans. VLSI Syst.

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Optimization-simulation loop-based method is popular and efficient in design migration/reuse automation. However, it is only restricted to be used in block-level due to the complexity of current mixed-signal system. This paper presents a hierarchical methodology for efficiently migrating mixed-signal circuit design from one technology node to another, while keeping the same circuit and layout topologies. It utilizes two stages of optimization processes to automatically resize and refine device dimensions in target technology. In the first stage, to avoid the costly simulation time without scarifying systematical functionality, only one block is represented in transistor level (TL), while other blocks are replaced with behavioral models. The multistart global optimization technique is applied to resize the TL block in systematic connection. This stage provides a good initial point for next system-level refinement. Moreover, for obtaining a process and parasitic closure solution, both parasitic and process variation effects are explored and used to constrain the schematic migration. A representative mixed-signal system, charge-pump phase-locked loop, is used to validate the proposed methodology. The experimental results show that the proposed methodology efficiently generates quality designs in target technology with much less simulation iterations, when comparing with recent available approaches. IndexTerms-Design reuse, optimization method, phase-locked loop (PLL), technology migration.

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“…Generating a layout from a given circuit is the obvious final step to tackle in order to accomplish a higher degree of automation in analog circuit design. Graupner et al [GJW11] presented a generator based approach, which is based on executable design flow descriptions. This translates to a programming inspired analog circuit design approach by providing a set of procedures and functionalities, which may be used to describe the steps to be taken in order to generate a target circuit.…”

Section: State-of-the-art In Analog Synthesismentioning

confidence: 99%

FEATS: Framework for Explorative Analog Topology Synthesis

Meißner

Hedrich

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The presented work inside this thesis aims to raise the degree of automation in analog circuit design. Therefore, a framework was developed to provide the necessary mechanisms in order to carry out a fully automated analog circuit synthesis, i.e., the construction of an analog circuit fulfilling all previously defined (electrical) specifications.Nowadays, analog circuit design in general is a very time consuming process compared to a digital design flow. Due to its discrete nature, the digital design process is highly automated and thus very efficient compared to analog circuit design. In modern Very-Large-Scale integration (VLSI) circuits the analog parts are mostly just a small portion of the overall chip area. Although this small portion is known to consume a major part of the needed workforce. Paired with product cycles which constantly get shorter, the time needed to develop the analog parts of an integrated circuit (IC) becomes a determinant factor. Apart from this, the ongoing progress in semiconductor processing technologies promises more speed with less power consumption on smaller areas, forcing the IC developers to keep track with the technology nodes in order to maintain competitiveness. Analog circuitry exhibits the inherent property of being hard to reuse, as porting from one technology node to another imposes critical changes for operating conditions (e.g., supply voltage) -mostly leading to a full redesign for most of the analog modules. This productivity gap between digital and analog design resembles the primary motivation for this thesis.Due to the availability of commercial sizing tools, this work deliberately focuses on the construction of circuit topologies in distinction to parameter synthesis, which can be obtained with a dedicated sizing tool. The focus on circuit construction allows the development of a framework which allows a full design space exploration. This thesis describes the needed concepts and methods to realize a deterministic, explorative analog synthesis framework. Despite this, a reference implementation is presented, which demonstrates the applicability in current analog design flows. circuit (c) a circuit representing a physical realization circuits (C) an unordered set of circuits design space (DS) design space seen as crossproduct of P S and ST S devices (M ) an unordered set of devices equivalence class (eqcls) an unordered set of objects sharing the combination set of invariant properties equivalence classes (EQCLS(c)) set of equivalence classes associated with the circuit c graph (G) a representation of object vertices connected through edges ground (V GN D ) name of the reference net or simply ground hash (hash(x)) hash associated with object x integer (N) integer numbers invariant properties (EQP ROP S(x)) set of invariant properties associated with x invariant property (p) a property associated with a specific IV i invariants (IV) an unordered set of invariants label (L(x)) label associated with object x nets (N ) an unordered set of nets parameter space ...

show abstract

Generator based approach for analog circuit and layout design and optimization

Cited by 14 publications

References 5 publications

Analog layout automation via self-organization: Enhancing the novel SWARM approach

Analog layout automation via self-organization: Enhancing the novel SWARM approach

Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework

FEATS: Framework for Explorative Analog Topology Synthesis

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