Generic Systolic Array for Run-Time Scalable Cores

Otero, Andrés; Krasteva, Yana Esteves; Torre, Eduardo de la; Riesgo, Teresa

doi:10.1007/978-3-642-12133-3_4

Cited by 6 publications

(7 citation statements)

References 13 publications

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“…Another characteristic that can be very useful to certain applications is the copy and paste property, from a position in the internal memory, to a different one. This can be very useful in applications like the scalable coprocessors shown in [20]. An important structural difference, compared with other approaches, is that this solution, instead of relocating partial bitstreams, headers and tails of the bitstreams are self-generated internally, and only pure configuration data is given as input.…”

Section: Hardware Reconfiguration Enginementioning

confidence: 99%

Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs

Otero

Llinás

Lombardo

et al. 2011

VLSI Circuits and Systems V

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Modern FPGAs with run-time reconfiguration allow the implementation of complex systems offering both the flexibility of software-based solutions combined with the performance of hardware. This combination of characteristics, together with the development of new specific methodologies, make feasible to reach new points of the system design space, and make embedded systems built on these platforms acquire more and more importance. However, the practical exploitation of this technique in fields that traditionally have relied on resource restricted embedded systems, is mainly limited by strict power consumption requirements, the cost and the high dependence of DPR techniques with the specific features of the device technology underneath. In this work, we tackle the previously reported problems, designing a reconfigurable platform based on the low-cost and low-power consuming Spartan-6 FPGA family. The full process to develop the platform will be detailed in the paper from scratch. In addition, the implementation of the reconfiguration mechanism, including two profiles, is reported. The first profile is a low-area and low-speed reconfiguration engine based mainly on software functions running on the embedded processor, while the other one is a hardware version of the same engine, implemented in the FPGA logic. This reconfiguration hardware block has been originally designed to the Virtex-5 family, and its porting process will be also described in this work, facing the interoperability problem among different families.

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Section: Hardware Reconfiguration Enginementioning

confidence: 99%

Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs

Otero

Llinás

Lombardo

et al. 2011

VLSI Circuits and Systems V

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“…As a result, this n to easily provide ped so far. Another tain applications is ion in the internal be very useful in hown in [22]. This operation, like the gned following a der to easily adapt protocols, as well e the portability to bers of the same neration relies on a of the FPGA that more, an important approaches, is that l bitstreams, selfms internally, and as an input.…”

Section: Proposed Relocation Somentioning

confidence: 99%

A Modular Peripheral to Support Self-Reconfiguration in SoCs

Otero¹,

Morales-Cas²,

Portilla³

et al. 2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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Abstract-In this paper, a solution to support the run-time readback, relocation and replication of cores in embedded systems with dynamic and partial reconfiguration capabilities is presented. The proposal shows a peripheral structure that allows an easy integration and communication with the rest of the system, including an API to make the reconfiguration details to be more transparent to software applications. Differently to other proposals, all functionality is implemented in hardware, achieving a higher reconfiguration speed. In addition, different design decisions have been taken in order to increase the portability of the solution to existing and, possibly, future FPGAs. Finally, a use case is provided, which shows the features of this module applied to the run-time scaling of a hardware coprocessor.

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“…Also reconfigurable blocks including bus-macro connections to run-time bypass heterogeneous columns of the FPGA can be included in this category, as it is done in [13].…”

Section: Communication Modulesmentioning

confidence: 99%

“…Consequently, it is necessary to provide a design flow that allows the creation of new cores for specific purposes, by means of the adaptation of the template. Details of this design flow, as well as a numerical comparison with other proposals of the state-of-the-art, are provided in [13]. An important requirement to this design flow is the compatibility with the commercial Xilinx design flow.…”

Section: Scalable Coprocessor Design Flowmentioning

confidence: 99%

“…Differently from the existing solutions, this proposal, instead of being focused on offering solutions to a specific problem [9] [10] [12], is a generic template that can be tuned to solve different computational problems. The adaptation is carried out using a custom design-flow described in a previous work [13]. This work includes both hardware aspects, as well as software drivers to create and manage the cores.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs

Otero

Torre

Riesgo

et al. 2010

2010 International Conference on Field Programmable Logic and Applications

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Abstract-Multimedia Systems on Chip have high computational requirements, as well as significant flexibility demands. Flexibility can be related with the reusability of the cores in charge of the execution of computation-intensive tasks, but also with the run-time adaptation of these cores to the execution of time-variable tasks, or to changing system conditions. Among the run-time flexibility requirements of hardware IPs, functional scalability has been identified as an interesting feature. The proposal in this paper is to take advantage of the regularity and the high-processing capability of systolic arrays, to develop runtime functional scalable cores, making use of spatial scalability, by means of replicating and relocating basic processing elements of the array. The relocation process is performed using the dynamic-reconfiguration possibilities offered by commercial FPGAs. In this paper, an architectural template is proposed to develop systolic scalable coprocessors following this approach, together with its corresponding software drivers that may be executed within an embedded processor. In addition, a design flow is proposed to adapt the architectural template to different problems, together with some examples of scalable cores created following this design. This solution provides better results, regarding the reconfiguration time and the memory necessity overhead, compared with other dynamically scalable solutions.

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Generic Systolic Array for Run-Time Scalable Cores

Cited by 6 publications

References 13 publications

Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs

Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs

A Modular Peripheral to Support Self-Reconfiguration in SoCs

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs

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