No abstract

Abstract-This paper presents an FPGA emulation-based fast Network on Chip (NoC) prototyping framework, called Dynamic Reconfigurable NoC (DRNoC) Emulation Platform. The main, distinguishing, characteristic of this approach is that design exploration does not requires re-synthesis, accelerating the process. For this aim, partial reconfiguration capabilities of some state of the art FPGAs have been developed and applied. The paper describes all the building elements of the proposed solution: the used partial reconfiguration approach, the design space exploration framework itself, and the data measuring system. Results and a use case are shown.

Abstract-Reconfigurable HW, like FPGAs, can improve the processing systems performance as it has been demonstrated by several research groups. Usually, the inclusion of such elements in HW platforms for Wireless Sensor Networks (WSNs) has been rejected by designers, mainly due to the power consumption penalization. A reconfigurable device allows not only performance improvement but also remote HW reconfiguration of the WSN node. In this paper, a entire working flow for generate, remotely configure and reconfigure the HW in a target custom reconfigurable platform developed at CEI (Centro de Electronica Industrial) is presented. The custom platform includes a microprocessor and an FPGA (Xilinx partially reconfigurable) to carry out all the processing tasks. The current reconfiguration process works with the JTAG interface, which makes the solution portable to other FPGAs, especially those new less power consuming devices that are appearing in the market nowadays.

No abstract

Abstract-Multimedia Systems on Chip have high computational requirements, as well as significant flexibility demands. Flexibility can be related with the reusability of the cores in charge of the execution of computation-intensive tasks, but also with the run-time adaptation of these cores to the execution of time-variable tasks, or to changing system conditions. Among the run-time flexibility requirements of hardware IPs, functional scalability has been identified as an interesting feature. The proposal in this paper is to take advantage of the regularity and the high-processing capability of systolic arrays, to develop runtime functional scalable cores, making use of spatial scalability, by means of replicating and relocating basic processing elements of the array. The relocation process is performed using the dynamic-reconfiguration possibilities offered by commercial FPGAs. In this paper, an architectural template is proposed to develop systolic scalable coprocessors following this approach, together with its corresponding software drivers that may be executed within an embedded processor. In addition, a design flow is proposed to adapt the architectural template to different problems, together with some examples of scalable cores created following this design. This solution provides better results, regarding the reconfiguration time and the memory necessity overhead, compared with other dynamically scalable solutions.