Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems

Krasteva, Yana Esteves; Torre, Elena; Riesgo, Teresa; Joly, Didier

doi:10.1109/fpl.2006.311298

Cited by 35 publications

(13 citation statements)

References 4 publications

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“…Another solution is presented in [28] with direct bitstream manipulation. In order to locate the components such as configurable logic blocks (CLBs) and block random access memory (BRAMs) inside the bitstream, equations are required.…”

Section: Experimental Results and Analysismentioning

confidence: 99%

An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

Krill¹,

Ahmad²,

Amira³

et al. 2010

Signal Processing: Image Communication

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Section: Experimental Results and Analysismentioning

confidence: 99%

An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

Krill¹,

Ahmad²,

Amira³

et al. 2010

Signal Processing: Image Communication

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“…However, documentation for all but obsolete devices (i.e., Virtex) does not describe the internal structure of the FPGA configuration frames [Xilinx 2005]. Results reported in [Hübner et al 2007;Krasteva et al 2006;Note and Rannaud 2008;Steiner 2002] provide only partial information. The use of FDAT and the BAPI module allows discovery of the relation between the configuration of an arbitrary resource (logic, routing, IO etc) and the content of the configuration frames.…”

Section: Bitstream Api (Bapi) Modulementioning

confidence: 97%

“…FDAT uses the Xilinx XDL file data, which provides textformat (ASCII) data description of the design configuration for Xilinx FPGAs Ehliar and Liu 2007;Maslennikow and Soltan 2003;Raaijmakers 2007;Steiner 2008;Todorovich 2006]. FDAT implementation is based on Xilinx published datasheets [Xilinx 2005[Xilinx , 2007a[Xilinx , 2007b and documentation [Kalte and Porrmann 2006;Krasteva et al 2006;Steiner 2002;Steiner and Athanas 2004].…”

Section: Introductionmentioning

confidence: 99%

Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems

Kȩpa

Morgan

Kosciuszkiewicz

et al. 2010

ACM Trans. Reconfigurable Technol. Syst.

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The growth of the Reconfigurable Computing (RC) systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Low-level design tools are increasingly required for RC bitstream debugging and IP core design assurance, particularly in multiparty Partially Reconfigurable (PR) designs. While tools for low-level analysis of design netlists do exist, there is increasing demand for automated and customisable bitstream analysis tools.This article discusses the need for low-level IP core verification within PR-enabled FPGA systems and reports FDAT (FPGA Design Analysis Tool), a versatile, modular and open tools framework for low-level analysis and verification of FPGA designs. FDAT provides a set of high-level Application Programming Interfaces (APIs) abstracting the Xilinx FPGA fabric, the implemented design (e.g., placed and routed netlist) and the related bitstream. A lightweight graphic frontend allows custom visualisation of the design within the FPGA fabric. The operation of FDAT is governed by "recipe" scripts which support rapid prototyping of the abstract algorithms for system-level design verification. FDAT recipes, being Python scripts, can be ported to embedded FPGA systems, for example, the previously reported Secure Reconfiguration Controller (SeReCon) which enforces an IP core spatial isolation policy in order to provide run-time protection to the PR system.The paper illustrates the application of FDAT for bit-pattern analysis of Virtex-II Pro and Virtex-5 inter-tile routing and verification of the spatial isolation between designs.

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“…Among them, a further classification can be carried out depending on the processing approach, existing both embedded software and hardware solutions. Examples of software-based solutions are XPART, a C version derived from the set of JBits Java classes and pBITPOS [13], an embedded version of BITPOS. A good summary of software-based solutions is provided in [14].…”

Section: State Of the Artmentioning

confidence: 99%

A Modular Peripheral to Support Self-Reconfiguration in SoCs

Otero¹,

Morales-Cas²,

Portilla³

et al. 2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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Abstract-In this paper, a solution to support the run-time readback, relocation and replication of cores in embedded systems with dynamic and partial reconfiguration capabilities is presented. The proposal shows a peripheral structure that allows an easy integration and communication with the rest of the system, including an API to make the reconfiguration details to be more transparent to software applications. Differently to other proposals, all functionality is implemented in hardware, achieving a higher reconfiguration speed. In addition, different design decisions have been taken in order to increase the portability of the solution to existing and, possibly, future FPGAs. Finally, a use case is provided, which shows the features of this module applied to the run-time scaling of a hardware coprocessor.

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Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems

Cited by 35 publications

References 4 publications

An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems

A Modular Peripheral to Support Self-Reconfiguration in SoCs

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