2015
DOI: 10.1142/s0218126616400181
|View full text |Cite
|
Sign up to set email alerts
|

Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim

Abstract: With the shrinking feature size and increasing aspect ratios of interconnects in DSM chips, the coupling noise between adjacent interconnects has become a major signal integrity (SI) issue, giving rise to crosstalk failures. In older technologies, SI issues have been ignored because of high noise immunity of the CMOS circuits and the process technology. However, as CMOS technologies lower down the supply voltage as well as the threshold voltage of a transistor, digital designs are more and more susceptible to … Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Publication Types

Select...

Relationship

0
0

Authors

Journals

citations
Cited by 0 publications
references
References 2 publications
0
0
0
Order By: Relevance

No citations

Set email alert for when this publication receives citations?