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This paper presents an emerging theory on the effects of unavoidable process variations during the fabrication of MEMS and other microsystems. The effects of parametric variations on device performance and design yield of the microsystems devices are analyzed and presented. A novel methodology in the design cycle of MEMS and other microsystems is introduced. The methodology is based on the concept of worst-case analysis having colossal advantages to offer. This paper describes some steps of this methodology with elaborated results. Also described in this paper is how each step contributes to counteract the effects produced by the parametric variations in the product cycle of microsystems.

Noise effects in coupled interconnects, Le. crosstalk induced glitch and crosstalk induced delay can significantly impact the performance of deep sub-micron (DSM) chips. Therefore, in this paper distributed RLGC transient model of coupled interconnects has been developed that will be useful for analyzing such crosstalk noise effects in DSM chips. The model accuracy is quite comparable to the PSPICE simulation results and yet the simulation speed is at least 11 times faster than the latter.

With the shrinking feature size and increasing aspect ratios of interconnects in DSM chips, the coupling noise between adjacent interconnects has become a major signal integrity (SI) issue, giving rise to crosstalk failures. In older technologies, SI issues have been ignored because of high noise immunity of the CMOS circuits and the process technology. However, as CMOS technologies lower down the supply voltage as well as the threshold voltage of a transistor, digital designs are more and more susceptible to noise because of the reduction of noise margin. The genetic algorithms (GAs) have been applied earlier in different engineering disciplines as potentially good optimization tools and for various applications in VLSI design, layout, EDIF digital system testing and also for test automation, particularly for stuck-at-faults and crosstalk-induced delay faults. In this paper, an elitist GA has been developed that can be used as an ATPG tool for generating the test patterns for crosstalk-induced faults between on-chip aggressor and victim and as well as for stuck-at-faults. It has been observed that the elitist GA, when the fitness function is properly defined, has immense potential in extracting the suitable test vectors quickly from randomly generated initial patterns.