Geometrical and Structural Design Schemes for Trench-Shaped Vertical Channel Transistors Using Atomic-Layer Deposited In-Ga-Zn-O

Improvement in Short-Channel Effects and Bias-Stress Stability of Vertical Thin-Film Transistors Using Atomic-Layer-Deposited In–Ga–Sn–O Channels

“…Meanwhile, the values of μ FE of the fabricated Dev-A, Dev-B, and Dev-C were estimated to be 0.1, 0.5, and 4.2 cm 2 /(V s), respectively. These values were suggested to be far lower compared with those obtained from the conventional planar-channel devices. , Actually, the back-channel scattering has been reported to be a main origin to degrade the carrier mobility for the oxide-channel VTFT due to a considerable amount of defect sites and uneven surface roughness, which might be generated during the formation process of spacer sidewalls . Additionally, the back-channel scattering effect might worsen as the area of the channel defined on the uneven back-channel surface increases, causing significant deterioration in the transports of carriers.…”

“…18,19 Actually, the back-channel scattering has been reported to be a main origin to degrade the carrier mobility for the oxide-channel VTFT due to a considerable amount of defect sites and uneven surface roughness, which might be generated during the formation process of spacer sidewalls. 11 Additionally, the back-channel scattering effect might worsen as the area of the channel defined on the uneven back-channel surface increases, causing significant deterioration in the transports of carriers. Alternatively, the L ch and W ch of the IGTO VTFT fabricated in this work were designed as 150 nm and 30 μm, respectively, and thus, the W ch value was defined 200 times larger than L ch , which was limited by minimum feature size and design rule available for our process equipment.…”

“…These obtained RMS roughness values were found to be typically 50 times higher than those obtained from the back channel for the conventional planar TFTs and resulted from the physical ion bombardment and chemical residues generated during the plasma etching process for the formation of spacer patterns. 11 In other words, a large amount of bulk traps may be so additionally generated as to overwhelm the number of intrinsic trap sites in the IGTO channel layers prepared onto the macro-and microscopically damaged vertical sidewalls of the spacer patterns. Therefore, we also fabricated a planar-channel TFT with a conventional TGBC structure as a controlled device to investigate the effect of unique structural features on the device performance.…”

“…13 Moreover, the back-channel interfaces for the VTFTs, which correspond to vertical sidewalls of patterned spacers, are completely different from those for the conventional planar TFTs, and hence, the back-channel qualities have decisive impact on the device performance. 11 Thus, ultimately, it is strategically important to maximize the current drivability (C DR ) while minimizing the SCEs of the oxide VTFTs for practical applications.…”

“…From these structural advantages, the device feasibility of the VTFTs utilizing various oxide channel materials have previously been verified. − However, oxide-channel VTFTs with shorter L ch ’s of several hundreds of nanometers were reported to typically suffer from various short-channel effects (SCEs), which may have a devastating impact on device characteristics . Moreover, the back-channel interfaces for the VTFTs, which correspond to vertical sidewalls of patterned spacers, are completely different from those for the conventional planar TFTs, and hence, the back-channel qualities have decisive impact on the device performance . Thus, ultimately, it is strategically important to maximize the current drivability ( C DR ) while minimizing the SCEs of the oxide VTFTs for practical applications.…”