Geometrical Effects in the Electroless Metallization of Fine Metal Patterns

Putten, Andre M. T. van der; Bakker, J. W. G. de

doi:10.1149/1.2220799

Cited by 40 publications

(25 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This model, known as the mixed potential theory (MPT), has been described in detail elsewhere in connection with EL metal deposition inside via holes. 33,34 Metallization bias in this case is due to the breakdown at smaller, less densely packed features of the linear diffusional transport of EL bath components normally established during plating of larger or densely packed features. For these smaller, more isolated features, mass transport by nonlinear diffusion is considerably enhanced compared to linear diffusion.…”

Section: Resultsmentioning

confidence: 99%

Channel‐Constrained Electroless Metal Deposition on Ligating Self‐Assembled Film Surfaces

Chen

Brandow

Dulcey

et al. 1999

J. Electrochem. Soc.

View full text Add to dashboard Cite

The ability to fabricate spatially well-defined, patterned, metal films on various substrates is critically important for numerous microelectronics applications. For example, fabrication of metal contacts and conductors is required in microwave circuits, printed wiring board (PWB) circuitry, local and global chip interconnects, and other aspects of electronics packaging technology. 1 Metal patterns are routinely used to define the opaque regions of reticles and masks for optical and X-ray lithography. Thin metal films have also been used as protective layers for pattern transfer in integrated circuit (IC) lithography due to the extremely high etching resistance of metals and/or oxides derived from elements such as titanium, 2 tungsten, 3 zirconium, 4 and nickel. 5 Many processes exist for metal pattern fabrication. Metal deposition techniques include sputtering, evaporation, chemical vapor deposition, electrolytic deposition, and electroless (EL) deposition. Of these, EL deposition 6 is particularly attractive in manufacturing because it offers the ability to metallize nonplanar, insulating substrates with low-temperature processes using simple materials and equipment at low cost. Approaches for producing lithographic patterns of metals are of two general classes: subtractive and additive. The traditional lift-off method is an example of a subtractive process wherein metal is initially homogeneously deposited over an exposed and developed photoresist; the remaining resist must then be stripped to remove metal from the regions where it is not required. Additive metallization is a simpler and less wasteful approach having distinct advantages in ease of processing and cost. A typical example of this approach involves initial deposition of a thin, homogeneous metal layer (by any of the above-mentioned techniques) onto a substrate, followed by lithographic patterning of a resist to block selected regions of the underlying metal film. The exposed metal underlayer serves as either an electrode for electrolytic 7 up-plating or as a catalytic region for EL metal deposition. 8 However, even with these approaches, the initial thin metal layer can lead to significant problems in the ultimate device structures, and subtractive steps must again be used to remove the buried metal. We therefore sought to develop an alternative process utilizing photolithography and molecular self-assembly together to spatially control the binding of a Pd EL catalyst to a substrate and initiate EL metal deposition in a fully additive manner.We have previously shown that self-assembled (SA) films of organosilanes containing ligand functional groups such as phosphines, pyridines, or alkylamines are useful for binding Pd catalysts to surfaces and that the bound catalysts initiate EL deposition. 9-12 These films are formed by chemisorption of alkoxysilane or chlorosilane precursors (typically of formula R n SiX 4Ϫn , where R contains the ligating group, X ϭ Cl, OCH 3 , or OC 2 H 5 , and n ϭ 1-3) to hydroxyl groups on the surface of various substrates...

show abstract

Section: Resultsmentioning

confidence: 99%

Channel‐Constrained Electroless Metal Deposition on Ligating Self‐Assembled Film Surfaces

Chen

Brandow

Dulcey

et al. 1999

J. Electrochem. Soc.

View full text Add to dashboard Cite

show abstract

“…[26][27][28][29][30][31] The NITD method is designed to selectively reduce metal ions only within a heating zone in the gap between the heater and the substrate, as shown in Fig. 1.…”

Section: Methodsmentioning

confidence: 99%

Defect-Free Copper Filling Using Nonisothermal Electroless Deposition with Fluorocarbon Surfactant

Chou

Sung

Liu

et al. 2008

J. Electrochem. Soc.

View full text Add to dashboard Cite

Electroless copper bottom-up filling of patterned substrates using nonisothermal deposition ͑NITD͒ with the addition of adequate surfactant was demonstrated. Combining the inhibitive ability of adequate surfactant with the higher driving force of NITD method, superfill of vias or trenches using only one inhibitor in the copper damascene of integrated circuits ͑ICs͒ was achieved. We tested several commercial surfactant agents and found that fluorinated alkyl quaternary ammonium iodides ͑FC͒ is best compatible to our NITD method. Void-free copper-filled features can be obtained by introducing the surfactant FC into the electroless bath of NITD. Furthermore, using our method, the conductivity of copper film was not negatively affected. We conclude that the surfactant FC combined with NITD method is very promising for the applications in filling trenches and vias with copper films in the IC industry.Electroless plating can deposit a metal film from an ionic solution onto catalytic sites of a substrate without any external power supply and has been widely applied to microelectronic packaging and manufacturing of integrated circuits ͑ICs͒. 1-6 It has also received great attention for its lower tool cost, excellent step-coverage capability for via holes and trenches, lower process temperature, and capability to deposit a metal film on a nonconductive specimen after sensitization and activation treatments. [7][8][9] Copper is now used in place of conventional aluminum-based wiring in ultralarge-scale integrated logic devices. Its outstanding advantages of low electrical resistivity ͑1.67 ⍀ cm͒, high melting point ͑1085°C͒, and superior resistance against electromigration are very desirable for the electronic industry. 10,11 Moreover, copper electroless plating is a premium process to deposit copper lines or seedlayers in the process of IC patterning before copper electroplating.However, there are three often-seen problems in the technique of electroless plating. First, it needs to activate the barrier/SiO 2 /Si substrate using palladium ͑Pd͒ before copper electroless plating. The resistivity of Pd is ϳ10 ⍀ cm, and the temperature of some ordered solid solution phases of Cu-Pd are below 500°C. Therefore, in the copper damascene process, the interdiffusion of Pd into copper easily form an alloy that increases the resistivity and the resistance-capacitance delay effect during the postannealing process. 12,13 Second, the difficulty to control the unstable deposition reaction resulting from inadequate concentration of stabilizer is common in typical electroless plating. Keeping a constant quantity of stabilizer is also difficult in the process. 14,15 Third, with the increase of IC density and the shrinkage in IC dimension, completely stuffing the submicrometer or nanometer features becomes more and more important, and is always a difficult issue during the copper deposition process. When the aspect ratio ͑a ratio of trench depth to its width͒ is Ͼ3, voids or seams are usually inevitable in the filling, and to stuff the high-a...

show abstract

“…In the case where the working electrode is composed of an array of nanoelectrodes embedded in a dielectric matrix, nonlinear diffusion is assumed at the beginning of electrodeposition because of the formation of a hemispheric zone of diffusion for each pore; then the diffusion becomes linear as the deposit grows. 27 In our case, where a membrane with nanopores is used as a template, the empty depth of the pore within the membrane also should be taken into account, which leads to linear diffusion at the beginning of plating. Figure 3 sums up the shape evolution of the diffusion layers that can be encountered during nanowire synthesis within a porous membrane.…”

Section: Electrochemical Synthesis and Structure Characterization Of mentioning

confidence: 99%

Electrochemical Synthesis of Antimony Nanowires and Analysis of Diffusion Layers

Roy¹,

Fricoteaux²,

Yu-Zhang³

2001

j nanosci nanotechnol

View full text Add to dashboard Cite

Synthesis of an array of antimony nanowires was performed by electrodeposition within a porous polycarbonate membrane. The sizes of pores range from 30 to 400 nm in diameter and their densities vary from 2 x 10(+6) to 2 x 10(+9) pores/cm2. To obtain optimal conditions for nanowire preparation, plating behavior was investigated by a potentiostatic method with two types (continued or pulsed) of polarization. The chronoamperometry revealed that responses depend on the type of polarization and on the pore density of the membrane. With high-density membranes, the diffusion layers of each individual pore immediately overlap when they reach the external part of the membrane. This leads to an abrupt decrease of current intensity. This phenomenon is not observed with low-density membranes because of the greater distance between pores. This mechanism, which was investigated in antimony nanowire plating, is applicable to electrodeposition of other types of materials.

show abstract

Geometrical Effects in the Electroless Metallization of Fine Metal Patterns

Cited by 40 publications

References 3 publications

Channel‐Constrained Electroless Metal Deposition on Ligating Self‐Assembled Film Surfaces

Channel‐Constrained Electroless Metal Deposition on Ligating Self‐Assembled Film Surfaces

Defect-Free Copper Filling Using Nonisothermal Electroless Deposition with Fluorocarbon Surfactant

Electrochemical Synthesis of Antimony Nanowires and Analysis of Diffusion Layers

Contact Info

Product

Resources

About