Ternary Ni-based amorphous films can serve as a barrier layer for Cu interconnects in ultralarge-scale integration ͑ULSI͒ applications. In this paper, Ni-Mo-P films deposited on silicon wafers without a complicated pretreatment such as Pd activation were prepared using a nonisothermal deposition ͑NITD͒ method. The deposition solutions and operating conditions for preparing the Ni-Mo-P alloys are presented, and the effect of the concentration of MoO 4 2− added in electrolytes on the deposition rate is investigated. The surface morphology, microstructures, compositions, and electrical resistivity of the Ni-Mo-P deposits are also thoroughly examined. Based on the experimental results, the Ni-based ternary alloys produced by the NITD method contain high levels of both Mo and P, and the properties of Ni-Mo-P films are dependent on the concentration of molybdate in electrolytes. It is concluded that the Ni-Mo-P thin films produced by the proposed approach in this study are promising for the 60 nm technologies in ULSI.Copper is now the most reliable interconnect material to replace conventional aluminum-based wiring in ultralarge-scale integrated ͑ULSI͒ logic devices due to its low electrical resistivity, high melting point, slight electromigration, and little stress-induced voiding. 1-5 Unfortunately, there are still a few reliability issues which retard widespread application of Cu, such as difficulty of dry etching, poor adhesion to interlevel dielectrics, and contamination in silicon, which degrades the performance of electrical devices. To employ Cu interconnection in Si-based integrated circuits, development of an effective diffusion barrier is necessary to prevent Cu diffusion into silicon and to avoid degradation of devices. [6][7][8] Recently, ternary metallic barrier layers prepared by the electroless plating process have been widely investigated. Ternary Ni-based alloys, such as Ni-Mo-P, Ni-Re-P, and Ni-W-P, can serve as an effective diffusion barrier to obstruct Cu atoms from penetrating into silicon. 9-11 The electroless plating process for depositing such layers has received great attention from this research community due to its low tool cost, excellent step-coverage capability for filling highaspect-ratio features, low-temperature operating procedure, and high selectivity for the forthcoming sub-65 nm integrated circuits. 12-14 However, for inert substrates such as Si and silicides, it is necessary to deposit catalytic seeds prior to the electroless plating process. The catalytic precipitates are usually deposited in a tin-palladium colloidal solution or in a PdCl 2 acid solution for the activation treatment. 15,16 The Pd particles prepared by these methods easily aggregate to clusters in tens or hundreds of nanometer sizes. Thus, difficulty in manufacturing ultrathin diffusion barriers is expected, and the conductivity of these deposits would be reduced due to the presence of catalysts in the bath. 17-19 Therefore, it is desirable to eliminate the Pd activation step. It has been reported that high conte...
