Geometry, kinetics, and short length effects of electromigration in Mn doped Cu interconnects at the 32nm technology node

Christiansen, C.; Li, Baozhen; Angyal, M.; Kane, Terence; McGahay, V.; Wang, Yun Yu; Yao, Shaoning

doi:10.1109/irps.2012.6241856

Cited by 11 publications

(5 citation statements)

References 8 publications

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“…But more importantly, narrow Ru interconnected lines require a thinner barrier layer compared to copper interconnected lines. [301] Seong Jun Yoon et al demonstrated that maximizing the grain sizes in Ru interconnected lines can effectively lower the total line resistivity [302]. The total line resistivity has been successfully reduced by more than 30% by suppressing the grain boundary scattering effect.…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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Section: Metal Materials Interconnectmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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“…However, scaling can significantly reduce the electromigration (EM) lifetime for Cu interconnects, raising serious reliability concern for advanced technology nodes. Some improvements have been developed to improve EM and to extend the technology node by using CoWP metal cap [247,248] and Mn alloying [249][250][251].…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

“…A self-forming barrier uses a Cu-X alloy-based seed layer to form the barrier layer by post metallization annealing. Among the tested alloying elements are V, Al, and Mn [249][250][251]271,272]. Mn-based self-formed barrier (SFB) is an attractive alternative technique from RC performance point of view.…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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“…For example, alloying element Mn can enhance EM performance through forming a metallic-state Mn-rich Cu layer at the interface to stop copper diffusion [2]. The degrees of EM enhancement can also vary with line width and electron flow direction [3]. Different effects are induced by alloying elements in Cu interconnect.…”

Section: Introductionmentioning

confidence: 99%