No abstract

Via impact on the upstream electromigration (EM) of low-k Cu interconnects was investigated based on 40/45nm technology node. It is found that via height is the main factor to affect EM performance. Increasing via height can lead to more early failure. Besides, alloy seed layer and argon power during via deposition are also observed to be two important factors to affect EM lifetime.

Traditionally, to assess reliability lifetimes and to evaluate reliability performance of semiconductor devices and chips, we test the samples to their failures. This can be called the "Test-to-Fail" scenario, which usually takes a long time (e.g., longer than a week). The Test-to-Failure scenario is required especially at the qualification stage, whose objective is to obtain the lifetimes of, e.g., devices, dielectrics, and metal lines. Due to the long test times, this approach is inadequate for reliability monitors, which need to be completed in a much shorter period of time so the product shipment will not be delayed and, if failed, timely corrective actions can be taken. Therefore, we are in urgent need of a much more efficient method to judge if the monitor meets reliability requirements. The "Test-to-Target" reliability test methodology perfectly matches such demand by only stressing the samples to much shorter times and can be applied on most common reliability tests like NBTI (Negative Bias Temperature Instabilities), HCI (Hot Carrier Injection), TDDB (Time Dependent Dielectric Breakdown), Isothermal EM test, and IMD (Inter Metal Dielectric) V ramp test. The corresponding specs for the Test-toTarget approach are defined based on the baseline records from the former complete Test-to-Fail reliability tests. From practical exercises after a long time, we prove the Test-to-Target methodology a truly useful approach particularly effective for reliability monitors, inline reliability assessments, process change management, nonconformance dispositions, and tool releases.

No abstract

Electromigration (EM) is one of the major indices to evaluate the reliability performance in IC devices. From the point of view of permutation and combination, there are many combination types for temperature and current density that used to determine the model parameters (Ea and n) in EM. Fourteen types among these combinations are chosen for this study and confidence intervals for model parameters are used as theoretical criteria. The study shows the most popular stress combination type is not the best one both from theory and experiment. Also, it is found that the tight confidence interval is a trade off for either the equipment capacity or the test cycle time in choosing the stress condition combination. Further, we recommend the appropriate stress combination types to be implemented in the experiment in order to save capacity and/or shorten test cycle time with still acceptable confidence interval.