GIDL in Doped and Undoped FinFET Devices for Low-Leakage Applications

Kerber, P.; Zhang, Qintao; Koswatta, Siyuranga O.; Bryant, A.

doi:10.1109/led.2012.2224089

Cited by 60 publications

(20 citation statements)

References 6 publications

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“…3(a). All resistance components of pFinFETs were extracted using [12] at the same overdrive voltage (V ov = V gs -V th ) of −0.7 V, where V th is the threshold voltage extracted using constant current method at 10 −8 W e f f /L g at the drain voltage of −0.05 V. The lightly-doped overlap/underlap regions reduce BTBT currents and R sd , and improve short-channel characteristics significantly [13], [14]. However, I on values for the L ov of −5.0 nm decrease greatly.…”

Section: Device Structure and Simulationsmentioning

confidence: 99%

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

Yoon

Jeong

Baek

et al. 2015

IEEE Electron Device Lett.

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DC/AC characteristics of Si bulk FinFETs including middle-of-line levels are precisely investigated using well-calibrated 3-D device simulations for system-on-chip applications. Scaling the fin widths down to 5 nm effectively enhances gate-to-channel controllability and improves RC delay, but a dramatic increase in band-to-band tunneling currents from source-to-drain does not satisfy low-power application in the 7-nm node. All lightly-doped extension regions as a solution could improve band-to-band tunneling currents and total gate capacitances because of better short-channel immunity and lower parasitic capacitances, respectively. Using systematic TCAD-based RC calculation, we suggest optimized overlap/ underlap lengths in the 7-nm node FinFETs to overcome the scaling limitations.

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Section: Device Structure and Simulationsmentioning

confidence: 99%

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

Yoon

Jeong

Baek

et al. 2015

IEEE Electron Device Lett.

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“…With the development of high-klmetal gate technology and the application of low supply power voltage, punch through leakage is becoming one of the primary components of the off-state current of FinFETs [1] (Figure l(a) shows the punch through leakage in the n-type FinFET (nFET) device which accounts for more than 90% of the device total off-state current). The punch through leakage mainly occurs below the device channel and is a part of the source-drain leakage current caused by drain voltage [2].…”

Section: Introductionmentioning

confidence: 99%

Punch through stop layer optimization in bulk FinFETs

Liu

Zhang

et al. 2014

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

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Punch through leakage is a main component of off state leakage in bulk FinFETs and it is usually suppressed by forming a punch through stop layer (PTSL). With triangular fms being used in 1 s t generation FinFET industrial volume production, this paper focuses on PTSL process optimization for FinFETs with triangular-shaped fins. The conditions of PTSL implantation are optimized and the sequence of PTSL formation process (before fin formation versus after fin formation) has been explored for the 1 s t time. The resultant n-type FinFETs (nFETs) exhibit low off-state leakage of 1.5 nAiurn, steep sub-threshold slope of 66 m V Idec and outstanding DIBL which are better than that of the previously reported 22 urn FinFETs.

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“…[4][5][6] Recently, the nanoscale FETs adapting steep junction gradients (L j ) and lightly-doped underlap structure are suggested to minimize gate-induced drain leakage and short channel degradation, and to improve AC performance by reducing parasitic capacitances. 7,8 Especially, GAA Si nanowire FETs have great potential to enable short channel immunity and DC/AC performance enhancement by encircling all around the channel under 7-nm regime. 9 Therefore, the analysis for RDF effects to GAA Si nanowire FETs with different L j values is significant to provide the device design guideline to optimize both DC/AC performance and variability concerns.…”

mentioning

confidence: 99%

Variability study of Si nanowire FETs with different junction gradients

et al. 2016

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Random dopant fluctuation effects of gate-all-around Si nanowire field-effect transistors (FETs) are investigated in terms of different diameters and junction gradients. The nanowire FETs with smaller diameters or shorter junction gradients increase relative variations of the drain currents and the mismatch of the drain currents between source-drain and drain-source bias change in the saturation regime. Smaller diameters decreased current drivability critically compared to standard deviations of the drain currents, thus inducing greater relative variations of the drain currents. Shorter junction gradients form high potential barriers in the source-side lightly-doped extension regions at on-state, which determines the magnitude of the drain currents and fluctuates the drain currents greatly under thermionic-emission mechanism. On the other hand, longer junction gradients affect lateral field to fluctuate the drain currents greatly. These physical phenomena coincide with correlations of the variations between drain currents and electrical parameters such as threshold voltages and parasitic resistances. The nanowire FETs with relatively-larger diameters and longer junction gradients without degrading short channel characteristics are suggested to minimize the relative variations and the mismatch of the drain currents.

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GIDL in Doped and Undoped FinFET Devices for Low-Leakage Applications

Cited by 60 publications

References 6 publications

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

Punch through stop layer optimization in bulk FinFETs

Variability study of Si nanowire FETs with different junction gradients

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