Variability study of Si nanowire FETs with different junction gradients

Abstract

Random dopant fluctuation effects of gate-all-around Si nanowire field-effect transistors (FETs) are investigated in terms of different diameters and junction gradients. The nanowire FETs with smaller diameters or shorter junction gradients increase relative variations of the drain currents and the mismatch of the drain currents between source-drain and drain-source bias change in the saturation regime. Smaller diameters decreased current drivability critically compared to standard deviations of the drain currents, thus inducing greater relative variations of the drain currents. Shorter junction gradients form high potential barriers in the source-side lightly-doped extension regions at on-state, which determines the magnitude of the drain currents and fluctuates the drain currents greatly under thermionic-emission mechanism. On the other hand, longer junction gradients affect lateral field to fluctuate the drain currents greatly. These physical phenomena coincide with correlations of the variations between drain currents and electrical parameters such as threshold voltages and parasitic resistances. The nanowire FETs with relatively-larger diameters and longer junction gradients without degrading short channel characteristics are suggested to minimize the relative variations and the mismatch of the drain currents.

Optimization of nanosheet number and width of multi-stacked nanosheet FETs for sub-7-nm node system on chip applications

“…Both PFETs and NFETs have larger proportions of I on for the top NS channels, but those for PFETs are higher. The top NS channels of the PFETs have greater S/D doping penetrations, affected by the S/D epi above the NS channels, making V th smaller 2,30) and the top NS channels are turned on at smaller V gs than the other NS channels. NFETs have small S/D doping concentrations, and thus all the NS channels are turned on at a similar V th .…”

DC Performance Variations of SOI FinFETs with Different Silicide Thickness

“…Figure 1 shows the possible variability sources of the S/D regions. Uneven NiSi/Si interface [14] and random dopant fluctuation (RDF) [15,16] can also fluctuate the contact resistivity and thus induce the DC performance variations. Different NiSi/Si contact area by different sili would also affect the DC performance and variations because typical transfer lengths, defined as the distances that carriers below the contact travel before entering into the contact, of SOI devices are in the order of 100 nm [17,18], which is longer than ext .…”

“…Several parameters from the transfer characteristics are extracted to analyze the DC performance variations: th , lowfield-mobility-related coefficient ( 0 ), and parasitic resistance ( sd ). th values are extracted using CCM or -function method [16,22]. th CCM is measured at th = eff / ⋅10 −8 A, whereas th from -function method ( th ) is extracted from the -axis intercept of the linearly extrapolated curve as shown in Figure 3.…”

A vertical-gaussian doped soi-tfet with enhanced dc and analog/rf performance

“…The UD-SOI-TFET uses the top lateral contact for both the source and the drain regions while the VG-SOI-TFET uses a side contact for the source and the top lateral contact for the drain region. The minimum g value is set to 1 nm/decade [28][29][30] at N p = 1×10 19 cm −3 while at smaller N p =5×10 18 cm −3 , it is chosen to be g=2 nm/decade, to ensure the drain contact remains ohmic in VG-SOI-TFET. The maximum g value of 5 nm/decade is chosen for both the case.…”