GIDL Increase Due to HCI Stress: Correlation Study of MOSFET Degradation Parameters and Modelling for Reliability Simulation

Ceccarelli, Edoardo; Manning, Kevin; Maxwell, S.L.; Heffernan, Colm

doi:10.1109/irps.2019.8720590

Cited by 7 publications

(1 citation statement)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To improve ERS efficiency, holes h can be generated by gate‐induced drain leakage (GIDL) intentionally made in transistors for a string selection and supplied to each cell. [ 92,93 ] This process will erase the entire block at once, or will be iterated through multiple steps of erase‐and‐verify. For programming, the page‐wise data dumping discussed in Section 3 can also be used.…”

Section: Device Configuration: 2d Vs 3d V‐nandmentioning

confidence: 99%

Review of Semiconductor Flash Memory Devices for Material and Process Issues

et al. 2022

View full text Add to dashboard Cite

Vertically integrated NAND (V‐NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176‐layer‐stacked V‐NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400–500) due to the total allowable chip thickness, which will be reached within 6–7 years. This review summarizes the current status and critical challenges of charge‐trap‐based flash memory devices, with a focus on the material (floating‐gate vs charge‐trap‐layer), array‐level circuit architecture (NOR vs NAND), physical integration structure (2D vs 3D), and cell‐level programming technique (single vs multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices.

show abstract

Section: Device Configuration: 2d Vs 3d V‐nandmentioning

confidence: 99%