Gigabit age microelectronics and their manufacture

Chatterjee, P.K.; Larrabee, Graydon B.

doi:10.1109/92.219903

Cited by 30 publications

(7 citation statements)

References 5 publications

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“…These costs do not include development costs, land, or corporate overhead allocated to the actual planning and construction of the fab. Nevertheless, the capital costs are roughly consistent with anticipated costs of about $1 billion for 200-mm wafer fabs running sub-half-micrometer CMOS processes with capacities of 30 000 wafers per month [7].…”

Section: B Fixed Costsmentioning

confidence: 72%

“…Cycle time is an important performance parameter for several reasons [7], [18]- [21]. Decreasing the cycle time in a fab can in turn decrease work-in-process inventory, which frees money that otherwise would have been necessary to sustain the inventory.…”

Section: B Objectivementioning

confidence: 99%

“…processing, along with the other innovations described above [7]. This paper will focus specifically on the effects of integrated single-wafer processing on fab cost and cycle time.…”

Section: Introductionmentioning

confidence: 98%

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Cost and cycle time performance of fabs based on integrated single-wafer processing

Wood

1997

IEEE Trans. Semicond. Manufact.

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Visions of future wafer fabs include the use of integrated single-wafer processors to achieve fast cycle times and contain rising production costs. A survey of IC manufacturers, equipment vendors, and IC manufacturing literature was used to generate hypothetical conventional and alternative fabs to evaluate the effect of integrated single-wafer processing on cycle time and cost performance. The distinguishing features of the alternative fab are 1) all thermal processes performed on singlewafer processors; 2) back-end wet cleans performed on singlewafer processors; 3) integration of single-wafer processors into clusters or cells wherever practical, and 4) extensive use of insitu insitu insitu process monitors to replace in-line process monitors. Modeling and simulation of the resulting fabs suggest that integrated singlewafer processing can reduce the cycle time of conventional fabs by about 50% without having a significant effect on wafer production cost. Tool integration and single-wafer processing must be used together to achieve these performance improvements. Although traditional lot sizes appeared to be appropriate for both fabs, improvements in cluster tool reliability and process step similarity could change optimal integrated tool configurations and reduce optimal lot sizes in the future.

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Section: B Fixed Costsmentioning

confidence: 72%

Section: B Objectivementioning

confidence: 99%

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Cost and cycle time performance of fabs based on integrated single-wafer processing

Wood

1997

IEEE Trans. Semicond. Manufact.

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“…Ten years after the first operational transistor was made of single dislocations there is no company that produces these devices. In considering the similarities between the genesis of mainstream electronics [27] and development of dislocation electronics one should remember that sales of dislocation components have yet to occur. Applying the CS evaluation principle, one can conclude that dislocation electronics have not reached maturity, probably, for fundamental reasons.…”

Section: The Small(est) Transistormentioning

confidence: 99%

Dislocations in Microelectronics

Mil’shtein

1999

phys. stat. sol. (a)

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“…These products require all of the features of deep submicron CMOS, namely high integration and performance at low power. The cost of computing has decreased by several orders of magnitude during the past two decades as indicated in Fig.1 [2]. With the advancement of technology, the mainstream computing platform has changed from traditional mainframes and minicomputers, to desktops and laptops.…”

Section: Introductionmentioning

confidence: 99%

Technology leverage for ultra-low power information systems

Stork

1995

Proc. IEEE

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Many applications for future generations of logic and memory chips will be requiring highly sophisticated computing functions at low cost. Small form factors, portability, and low cost will require low power operation. While continued scaling of silicon technology to dimensions below quarter micron devices and interconnections appears technically feasible, higher levels of integration and operation at higher speed have been driving the power consumption of logic chips up instead of down. This paper discusses how scaled submicron silicon technology can provide leverage to reduce power, while gaining in throughput for logic chips, and in capacity for memory functions. Strong reductions in voltage supply have to accompany shrinking dimensions. Materials limits such as tunneling currents through ultra-thin silicon-dioxide gate dielectrics and electromigration in minimum pitch interconnections emerge to be key challenges to realize low power 0.1 µm level CMOS circuits. A more than 10x gain in productivity as measured by the energy*delay product can be realized by shrinking from 0.5 to 0.125 µm CMOS device technology.

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Gigabit age microelectronics and their manufacture

Cited by 30 publications

References 5 publications

Cost and cycle time performance of fabs based on integrated single-wafer processing

Cost and cycle time performance of fabs based on integrated single-wafer processing

Dislocations in Microelectronics

Technology leverage for ultra-low power information systems

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