Glass‐substrate‐based high‐performance ZnO‐TFT by using a Ta₂O₅ insulator modified by thin SiO₂ films

Abstract

Thin SiO 2 films were used to modify the Ta 2 O 5 insulator (STS) in the ZnO-TFTs fabricated at room temperature by RF magnetron sputtering. The performance of the device was obviously improved after adding thin SiO 2 layers, such as: enhancement of on/off ratio by one order of magnitude, reduction of the subthreshold swing from 0.32 to 0.28 V/dec, increase of the field effect mobility (from 46.2 to 52.4 cm 2 /V s), as well as reduction of the hysteresis in I DS versus V GS curves and capacitance-voltage characteristics. The capacitancevoltage and C À2 versus voltage characteristics were investigated, from which the trapped charge density at or near the interface between insulator and ZnO layer as well as the carriers concentration of the ZnO film are calculated. The performance enhancements are attributed to the reduce of leakage current, smoother surface morphology, and suppress of charge trapping by using SiO 2 films to modify the high-k Ta 2 O 5 dielectric.

Effects of annealing temperature of NbLaO gate dielectric on electrical properties of ZnO thin-film transistor

“…The trap density at/near the gate-dielectric/ ZnO interface can be estimated by equation (3) to be 1.6×10 12 , 1.2×10 12 and 3.6×10 12 cm −2 for the annealing temperature of 200°C, 300°C and 400°C, respectively, indicating that the relatively good electrical performance of the ZnO-TFT with the annealing temperature of 300°C is mainly attributed to the low trap density at/near the gate-dielectric/ZnO interface. In addition, the devices for the three annealing temperatures exhibit a low voltage operation (<8 V), which is close to the results reported using Al 2 O 3 and Ta 2 O 5 gate dielectrics [11,27], but is higher than that of HfLaO and ZrO 2 gate dielectrics [19,20], implying that the electrical performances of the device need to be further optimized for the requirement of low power application in flexible and wearable electronics. Figure 4 exhibits the hysteresis behavior of transfer characteristics under forward and reverse V GS sweeps, and the threshold-voltage shifts (ΔV th =V th·reverse −V th·forward ) of the samples with different NbLaO annealing temperatures are listed in table 1.…”

“…As a result, V th is shifted in the negative direction to produce an anticlockwise hysteresis. However, it is notable that ΔV th of the sample annealed at 300°C (−0.48 V) is much smaller than those of the other two samples (−2.95 and −2.72 V) and close to or less than that of the ZnO TFTs with Al 2 O 3 or Ta 2 O 5 as gate dielectrics [27,28]. The large ΔV th of the sample annealed at 200°C should be due to the stronger moisture absorption of the looser NbLaO film annealed at lower temperature [22].…”

Sol‐gel derived TiNb2O7 dielectric thin films for transparent electronic applications

“…Although the low dielectric‐constant interfacial layers also reduce the dielectric constant, 34.86 (e.a.air‐300, this work) is higher than lots of high‐k materials under low temperature (smaller than 300°C) process, such as 10.4 for Al 2 O 3, 16 for Y 2 O 3, and 18 for Ta 2 O 5. In addition, Figure depicts the comparison of electrical properties between e.a.air‐300 and TiO 2 or Nb 2 O 5. The dielectric constant of e.a.air‐300 is comparable to the others, and the current density of it is more than one order of magnitude lower than TiO 2 and Nb 2 O 5 at 100 kV/cm stress.…”

Low Voltage a-IGZO Thin Film Transistor Using Tantalum Oxide by Thermal Oxidation

“…A tantalum oxide layer also has a large dielectric constant of 22 and has been applied as the gate insulator using various methods, such as sputtering, anodic oxidation, sol-gel, e-beam evaporation, thermal oxidation, and atomic layer deposition [18][19][20][21][22] . Threshold voltage reduction for organic TFTs was reported using anodized tantalum oxide as a gate insulator, and mobility of 0.36 cm 2 /V•s was obtained on a plastic substrate 18 .…”