Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processor

Hu, Weiwu; Zhang, Yifu; Yang, Liu; Fan, Baoxia; Chen, Tianshi; Zhong, Shaobin; Huandong, Wang; Qi, Zichu; Wang, Pengyu; Gao, Xiang; Xu, Yang; Xiao, B.L.; Wang, Hongsheng; Yang, Zongren; Liu, Yang; Chen, Shuai

doi:10.1109/isscc.2013.6487634

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Cited by 5 publications

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LAST: An Efficient In-place Static Binary Translator for RISC Architectures

Lan,

Hu,

Niu

et al. 2024

Lecture Notes in Computer Science

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LAST: An Efficient In-place Static Binary Translator for RISC Architectures

Lan,

Hu,

Niu

et al. 2024

Lecture Notes in Computer Science

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Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors

Usami

Kudo

Matsunaga

et al. 2014

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

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This paper presents a design and control scheme of a microprocessor whose internal function units are power gated at instruction-by-instruction basis. Enabling/disabling the power gating is adaptively controlled under the support of on-chip leakage monitors and the operating system to minimize energy overhead due to sleep-in and wakeup. Measured results of the fabricated chip in the 65nm CMOS technology demonstrated that our approach reduces energy to 21-35% in the range of 25-85 C as compared to the non power-gated case. Energy dissipation was reduced by up to 15% as compared to the conventional fine-grain power gating technique in the same temperature range.

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